mirror of
https://github.com/YosysHQ/yosys
synced 2026-03-03 12:16:56 +00:00
Merge branch 'main' into emil/turbo-celltypes
This commit is contained in:
nella
GitHub
commit
2a2c91e78a
265 changed files with 11258 additions and 3014 deletions
|
|
@ -18,10 +18,11 @@ endif
|
|||
|
||||
EXTRAFLAGS := -lyosys -pthread
|
||||
|
||||
OBJTEST := objtest
|
||||
BINTEST := bintest
|
||||
MAKEFILE_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST))))
|
||||
OBJTEST := $(MAKEFILE_DIR)objtest
|
||||
BINTEST := $(MAKEFILE_DIR)bintest
|
||||
|
||||
ALLTESTFILE := $(shell find . -name '*Test.cc' | sed 's|^\./||' | tr '\n' ' ')
|
||||
ALLTESTFILE := $(shell cd $(MAKEFILE_DIR) && find . -name '*Test.cc' | sed 's|^\./||' | tr '\n' ' ')
|
||||
TESTDIRS := $(sort $(dir $(ALLTESTFILE)))
|
||||
TESTS := $(addprefix $(BINTEST)/, $(basename $(ALLTESTFILE:%Test.cc=%Test.o)))
|
||||
|
||||
|
|
@ -34,7 +35,7 @@ $(BINTEST)/%: $(OBJTEST)/%.o | prepare
|
|||
$(CXX) -L$(ROOTPATH) $(RPATH) $(LINKFLAGS) -o $@ $^ $(LIBS) \
|
||||
$(GTEST_LDFLAGS) $(EXTRAFLAGS)
|
||||
|
||||
$(OBJTEST)/%.o: $(basename $(subst $(OBJTEST),.,%)).cc | prepare
|
||||
$(OBJTEST)/%.o: $(MAKEFILE_DIR)/%.cc | prepare
|
||||
$(CXX) -o $@ -c -I$(ROOTPATH) $(CPPFLAGS) $(CXXFLAGS) $(GTEST_CXXFLAGS) $^
|
||||
|
||||
.PHONY: prepare run-tests clean
|
||||
|
|
|
|||
47
tests/unit/kernel/modindexTest.cc
Normal file
47
tests/unit/kernel/modindexTest.cc
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
#include <gtest/gtest.h>
|
||||
|
||||
#include "kernel/modtools.h"
|
||||
#include "kernel/rtlil.h"
|
||||
|
||||
YOSYS_NAMESPACE_BEGIN
|
||||
|
||||
TEST(ModIndexSwapTest, has)
|
||||
{
|
||||
Design* d = new Design;
|
||||
Module* m = d->addModule("$m");
|
||||
Wire* o = m->addWire("$o", 2);
|
||||
o->port_input = true;
|
||||
Wire* i = m->addWire("$i", 2);
|
||||
i->port_input = true;
|
||||
m->fixup_ports();
|
||||
m->addNot("$not", i, o);
|
||||
auto mi = ModIndex(m);
|
||||
mi.reload_module();
|
||||
for (auto [sb, info] : mi.database) {
|
||||
EXPECT_TRUE(mi.database.find(sb) != mi.database.end());
|
||||
}
|
||||
m->swap_names(i, o);
|
||||
for (auto [sb, info] : mi.database) {
|
||||
EXPECT_TRUE(mi.database.find(sb) != mi.database.end());
|
||||
}
|
||||
}
|
||||
|
||||
TEST(ModIndexDeleteTest, has)
|
||||
{
|
||||
if (log_files.empty()) log_files.emplace_back(stdout);
|
||||
Design* d = new Design;
|
||||
Module* m = d->addModule("$m");
|
||||
Wire* w = m->addWire("$w");
|
||||
Wire* o = m->addWire("$o");
|
||||
o->port_output = true;
|
||||
m->fixup_ports();
|
||||
Cell* not_ = m->addNotGate("$not", w, o);
|
||||
auto mi = ModIndex(m);
|
||||
mi.reload_module();
|
||||
mi.dump_db();
|
||||
Wire* a = m->addWire("\\a");
|
||||
not_->setPort(ID::A, a);
|
||||
EXPECT_TRUE(mi.ok());
|
||||
}
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
61
tests/unit/kernel/rtlilStringTest.cc
Normal file
61
tests/unit/kernel/rtlilStringTest.cc
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
#include <gtest/gtest.h>
|
||||
|
||||
#include "kernel/rtlil.h"
|
||||
#include "kernel/yosys.h"
|
||||
|
||||
YOSYS_NAMESPACE_BEGIN
|
||||
|
||||
namespace RTLIL {
|
||||
|
||||
TEST(RtlilStrTest, DesignToString) {
|
||||
Design design;
|
||||
Module *mod = design.addModule(ID(my_module));
|
||||
mod->addWire(ID(my_wire), 1);
|
||||
|
||||
std::string design_str = design.to_rtlil_str();
|
||||
|
||||
EXPECT_NE(design_str.find("module \\my_module"), std::string::npos);
|
||||
EXPECT_NE(design_str.find("end"), std::string::npos);
|
||||
}
|
||||
|
||||
TEST(RtlilStrTest, ModuleToString) {
|
||||
Design design;
|
||||
Module *mod = design.addModule(ID(test_mod));
|
||||
Wire *wire = mod->addWire(ID(clk), 1);
|
||||
wire->port_input = true;
|
||||
|
||||
std::string mod_str = mod->to_rtlil_str();
|
||||
|
||||
EXPECT_NE(mod_str.find("module \\test_mod"), std::string::npos);
|
||||
EXPECT_NE(mod_str.find("wire"), std::string::npos);
|
||||
EXPECT_NE(mod_str.find("\\clk"), std::string::npos);
|
||||
EXPECT_NE(mod_str.find("input"), std::string::npos);
|
||||
}
|
||||
|
||||
TEST(RtlilStrTest, WireToString) {
|
||||
Design design;
|
||||
Module *mod = design.addModule(ID(m));
|
||||
Wire *wire = mod->addWire(ID(data), 8);
|
||||
|
||||
std::string wire_str = wire->to_rtlil_str();
|
||||
|
||||
EXPECT_NE(wire_str.find("wire"), std::string::npos);
|
||||
EXPECT_NE(wire_str.find("width 8"), std::string::npos);
|
||||
EXPECT_NE(wire_str.find("\\data"), std::string::npos);
|
||||
}
|
||||
|
||||
TEST(RtlilStrTest, CellToString) {
|
||||
Design design;
|
||||
Module *mod = design.addModule(ID(m));
|
||||
Cell *cell = mod->addCell(ID(u1), ID(my_cell_type));
|
||||
|
||||
std::string cell_str = cell->to_rtlil_str();
|
||||
|
||||
EXPECT_NE(cell_str.find("cell"), std::string::npos);
|
||||
EXPECT_NE(cell_str.find("\\my_cell_type"), std::string::npos);
|
||||
EXPECT_NE(cell_str.find("\\u1"), std::string::npos);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
179
tests/unit/opt/optDffFindComplementaryPatternTest.cc
Normal file
179
tests/unit/opt/optDffFindComplementaryPatternTest.cc
Normal file
|
|
@ -0,0 +1,179 @@
|
|||
#include <gtest/gtest.h>
|
||||
#include "kernel/pattern.h"
|
||||
|
||||
YOSYS_NAMESPACE_BEGIN
|
||||
|
||||
class FindComplementaryPatternVarTest : public ::testing::Test {
|
||||
protected:
|
||||
RTLIL::Design *design;
|
||||
RTLIL::Module *module;
|
||||
RTLIL::Wire *wire_a;
|
||||
RTLIL::Wire *wire_b;
|
||||
RTLIL::Wire *wire_c;
|
||||
RTLIL::Wire *bus;
|
||||
|
||||
void SetUp() override {
|
||||
design = new RTLIL::Design;
|
||||
module = design->addModule(ID(test_module));
|
||||
wire_a = module->addWire(ID(a));
|
||||
wire_b = module->addWire(ID(b));
|
||||
wire_c = module->addWire(ID(c));
|
||||
bus = module->addWire(ID(bus), 4);
|
||||
}
|
||||
|
||||
void TearDown() override {
|
||||
delete design;
|
||||
}
|
||||
|
||||
RTLIL::SigBit bit(RTLIL::Wire *w, int offset = 0) {
|
||||
return RTLIL::SigBit(w, offset);
|
||||
}
|
||||
};
|
||||
|
||||
TEST_F(FindComplementaryPatternVarTest, EmptyPatterns) {
|
||||
pattern_t left, right;
|
||||
|
||||
auto result = find_complementary_pattern_var(left, right);
|
||||
EXPECT_FALSE(result.has_value());
|
||||
}
|
||||
|
||||
TEST_F(FindComplementaryPatternVarTest, IdenticalSingleVar) {
|
||||
pattern_t left, right;
|
||||
left[bit(wire_a)] = true;
|
||||
right[bit(wire_a)] = true;
|
||||
|
||||
auto result = find_complementary_pattern_var(left, right);
|
||||
EXPECT_FALSE(result.has_value());
|
||||
}
|
||||
|
||||
TEST_F(FindComplementaryPatternVarTest, ComplementarySingleVar) {
|
||||
pattern_t left, right;
|
||||
left[bit(wire_a)] = true;
|
||||
right[bit(wire_a)] = false;
|
||||
|
||||
auto result = find_complementary_pattern_var(left, right);
|
||||
ASSERT_TRUE(result.has_value());
|
||||
EXPECT_EQ(result.value(), bit(wire_a));
|
||||
}
|
||||
|
||||
TEST_F(FindComplementaryPatternVarTest, MissingKeyInRight) {
|
||||
pattern_t left, right;
|
||||
left[bit(wire_a)] = true;
|
||||
left[bit(wire_b)] = false;
|
||||
right[bit(wire_a)] = true;
|
||||
|
||||
auto result = find_complementary_pattern_var(left, right);
|
||||
EXPECT_FALSE(result.has_value());
|
||||
}
|
||||
|
||||
TEST_F(FindComplementaryPatternVarTest, TwoVarsOneComplementary) {
|
||||
pattern_t left, right;
|
||||
left[bit(wire_a)] = true;
|
||||
left[bit(wire_b)] = false;
|
||||
right[bit(wire_a)] = true;
|
||||
right[bit(wire_b)] = true;
|
||||
|
||||
auto result = find_complementary_pattern_var(left, right);
|
||||
ASSERT_TRUE(result.has_value());
|
||||
EXPECT_EQ(result.value(), bit(wire_b));
|
||||
}
|
||||
|
||||
TEST_F(FindComplementaryPatternVarTest, TwoVarsBothComplementary) {
|
||||
pattern_t left, right;
|
||||
left[bit(wire_a)] = true;
|
||||
left[bit(wire_b)] = false;
|
||||
right[bit(wire_a)] = false;
|
||||
right[bit(wire_b)] = true;
|
||||
|
||||
auto result = find_complementary_pattern_var(left, right);
|
||||
EXPECT_FALSE(result.has_value());
|
||||
}
|
||||
|
||||
TEST_F(FindComplementaryPatternVarTest, LeftSubsetOfRight) {
|
||||
pattern_t left, right;
|
||||
left[bit(wire_a)] = true;
|
||||
left[bit(wire_b)] = false;
|
||||
right[bit(wire_a)] = true;
|
||||
right[bit(wire_b)] = true;
|
||||
right[bit(wire_c)] = false;
|
||||
|
||||
auto result = find_complementary_pattern_var(left, right);
|
||||
ASSERT_TRUE(result.has_value());
|
||||
EXPECT_EQ(result.value(), bit(wire_b));
|
||||
}
|
||||
|
||||
TEST_F(FindComplementaryPatternVarTest, ThreeVarsAllSame) {
|
||||
pattern_t left, right;
|
||||
left[bit(wire_a)] = true;
|
||||
left[bit(wire_b)] = false;
|
||||
left[bit(wire_c)] = true;
|
||||
right[bit(wire_a)] = true;
|
||||
right[bit(wire_b)] = false;
|
||||
right[bit(wire_c)] = true;
|
||||
|
||||
auto result = find_complementary_pattern_var(left, right);
|
||||
EXPECT_FALSE(result.has_value());
|
||||
}
|
||||
|
||||
TEST_F(FindComplementaryPatternVarTest, PracticalPatternSimplification) {
|
||||
pattern_t pattern1, pattern2;
|
||||
pattern1[bit(bus, 0)] = true;
|
||||
pattern1[bit(bus, 1)] = true;
|
||||
pattern2[bit(bus, 0)] = true;
|
||||
pattern2[bit(bus, 1)] = false;
|
||||
|
||||
auto result = find_complementary_pattern_var(pattern1, pattern2);
|
||||
ASSERT_TRUE(result.has_value());
|
||||
EXPECT_EQ(result.value(), bit(bus, 1));
|
||||
|
||||
// Swapped args
|
||||
auto result2 = find_complementary_pattern_var(pattern2, pattern1);
|
||||
ASSERT_TRUE(result2.has_value());
|
||||
EXPECT_EQ(result2.value(), bit(bus, 1));
|
||||
}
|
||||
|
||||
TEST_F(FindComplementaryPatternVarTest, MuxTreeClockEnableDetection) {
|
||||
pattern_t feedback_path1, feedback_path2;
|
||||
feedback_path1[bit(wire_a)] = true;
|
||||
feedback_path1[bit(wire_b)] = true;
|
||||
feedback_path2[bit(wire_a)] = true;
|
||||
feedback_path2[bit(wire_b)] = false;
|
||||
|
||||
auto comp = find_complementary_pattern_var(feedback_path1, feedback_path2);
|
||||
ASSERT_TRUE(comp.has_value());
|
||||
EXPECT_EQ(comp.value(), bit(wire_b));
|
||||
|
||||
pattern_t simplified = feedback_path1;
|
||||
simplified.erase(comp.value());
|
||||
|
||||
EXPECT_EQ(simplified.size(), 1);
|
||||
EXPECT_TRUE(simplified.count(bit(wire_a)));
|
||||
EXPECT_TRUE(simplified[bit(wire_a)]);
|
||||
}
|
||||
|
||||
TEST_F(FindComplementaryPatternVarTest, AsymmetricPatterns) {
|
||||
pattern_t left, right;
|
||||
left[bit(wire_a)] = true;
|
||||
right[bit(wire_a)] = false;
|
||||
right[bit(wire_b)] = true;
|
||||
right[bit(wire_c)] = false;
|
||||
|
||||
auto result = find_complementary_pattern_var(left, right);
|
||||
ASSERT_TRUE(result.has_value());
|
||||
EXPECT_EQ(result.value(), bit(wire_a));
|
||||
}
|
||||
|
||||
TEST_F(FindComplementaryPatternVarTest, WireOffsetDistinction) {
|
||||
pattern_t left, right;
|
||||
left[bit(bus, 0)] = true;
|
||||
left[bit(bus, 1)] = false;
|
||||
right[bit(bus, 0)] = true;
|
||||
right[bit(bus, 1)] = true;
|
||||
right[bit(bus, 2)] = false;
|
||||
|
||||
auto result = find_complementary_pattern_var(left, right);
|
||||
ASSERT_TRUE(result.has_value());
|
||||
EXPECT_EQ(result.value(), bit(bus, 1));
|
||||
}
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
Loading…
Add table
Add a link
Reference in a new issue