mirror of
https://github.com/YosysHQ/yosys
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Merge branch 'main' into emil/turbo-celltypes
This commit is contained in:
nella
GitHub
commit
2a2c91e78a
265 changed files with 11258 additions and 3014 deletions
1
tests/aiger/.gitignore
vendored
1
tests/aiger/.gitignore
vendored
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/*_ref.v
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/neg.out/
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/gate/
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7
tests/aiger/gold/__ANDNOT__00000.aag
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7
tests/aiger/gold/__ANDNOT__00000.aag
Normal file
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|||
aag 3 2 0 1 1
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||||
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||||
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7
tests/aiger/gold/__AND__00000.aag
Normal file
7
tests/aiger/gold/__AND__00000.aag
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aag 3 2 0 1 1
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2
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6 4 2
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||||
Generated by Yosys
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||||
9
tests/aiger/gold/__AOI3__00000.aag
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9
tests/aiger/gold/__AOI3__00000.aag
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aag 5 3 0 1 2
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Generated by Yosys
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tests/aiger/gold/__AOI4__00000.aag
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tests/aiger/gold/__AOI4__00000.aag
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aag 7 4 0 1 3
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||||
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tests/aiger/gold/__BUF__00000.aag
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tests/aiger/gold/__BUF__00000.aag
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aag 1 1 0 1 0
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c
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||||
Generated by Yosys
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tests/aiger/gold/__MUX__00000.aag
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tests/aiger/gold/__MUX__00000.aag
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aag 6 3 0 1 3
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7
tests/aiger/gold/__NAND__00000.aag
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tests/aiger/gold/__NAND__00000.aag
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aag 3 2 0 1 1
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tests/aiger/gold/__NMUX__00000.aag
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tests/aiger/gold/__NMUX__00000.aag
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aag 6 3 0 1 3
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Generated by Yosys
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7
tests/aiger/gold/__NOR__00000.aag
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7
tests/aiger/gold/__NOR__00000.aag
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aag 3 2 0 1 1
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6 5 3
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c
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||||
Generated by Yosys
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5
tests/aiger/gold/__NOT__00000.aag
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5
tests/aiger/gold/__NOT__00000.aag
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aag 1 1 0 1 0
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c
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||||
Generated by Yosys
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tests/aiger/gold/__OAI3__00000.aag
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tests/aiger/gold/__OAI3__00000.aag
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aag 5 3 0 1 2
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Generated by Yosys
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11
tests/aiger/gold/__OAI4__00000.aag
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tests/aiger/gold/__OAI4__00000.aag
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aag 7 4 0 1 3
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c
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||||
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7
tests/aiger/gold/__ORNOT__00000.aag
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7
tests/aiger/gold/__ORNOT__00000.aag
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aag 3 2 0 1 1
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Generated by Yosys
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7
tests/aiger/gold/__OR__00000.aag
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7
tests/aiger/gold/__OR__00000.aag
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@ -0,0 +1,7 @@
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aag 3 2 0 1 1
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2
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6 5 3
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c
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||||
Generated by Yosys
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tests/aiger/gold/__XNOR__00000.aag
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tests/aiger/gold/__XNOR__00000.aag
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aag 5 2 0 1 3
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6 4 2
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10 9 7
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c
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||||
Generated by Yosys
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9
tests/aiger/gold/__XOR__00000.aag
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9
tests/aiger/gold/__XOR__00000.aag
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aag 5 2 0 1 3
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8 5 3
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c
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Generated by Yosys
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tests/aiger/gold/_add_00000.aag
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tests/aiger/gold/_add_00000.aag
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aag 51 4 0 8 47
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c
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||||
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tests/aiger/gold/_alu_00000.aag
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aag 33 5 0 9 28
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64 62 9
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66 65 61
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c
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||||
Generated by Yosys
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tests/aiger/gold/_and_00000.aag
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aag 17 11 0 8 6
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c
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tests/aiger/gold/_buf_00000.aag
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aag 6 6 0 6 0
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c
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||||
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tests/aiger/gold/_eq_00000.aag
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aag 38 11 0 5 27
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26 11 3
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28 27 25
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c
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||||
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c
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c
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c
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c
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c
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c
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|
||||
0
|
||||
20 19 10
|
||||
22 18 11
|
||||
24 23 21
|
||||
26 19 8
|
||||
28 17 6
|
||||
30 15 4
|
||||
32 12 3
|
||||
34 13 2
|
||||
36 35 32
|
||||
38 14 5
|
||||
40 39 37
|
||||
42 41 31
|
||||
44 16 7
|
||||
46 45 43
|
||||
48 47 29
|
||||
50 18 9
|
||||
52 51 49
|
||||
54 53 27
|
||||
56 55 23
|
||||
58 57 21
|
||||
60 59 24
|
||||
62 23 21
|
||||
64 57 21
|
||||
66 64 63
|
||||
68 67 61
|
||||
c
|
||||
Generated by Yosys
|
||||
10
tests/aiger/gold/_mux_00000.aag
Normal file
10
tests/aiger/gold/_mux_00000.aag
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
aag 6 3 0 1 3
|
||||
2
|
||||
4
|
||||
6
|
||||
13
|
||||
8 7 2
|
||||
10 6 4
|
||||
12 11 9
|
||||
c
|
||||
Generated by Yosys
|
||||
40
tests/aiger/gold/_ne_00000.aag
Normal file
40
tests/aiger/gold/_ne_00000.aag
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
aag 29 10 0 8 19
|
||||
2
|
||||
4
|
||||
6
|
||||
8
|
||||
10
|
||||
12
|
||||
14
|
||||
16
|
||||
18
|
||||
20
|
||||
59
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
22 12 2
|
||||
24 13 3
|
||||
26 25 23
|
||||
28 14 4
|
||||
30 15 5
|
||||
32 31 29
|
||||
34 33 27
|
||||
36 16 6
|
||||
38 17 7
|
||||
40 39 37
|
||||
42 41 34
|
||||
44 18 8
|
||||
46 19 9
|
||||
48 47 45
|
||||
50 49 42
|
||||
52 20 10
|
||||
54 21 11
|
||||
56 55 53
|
||||
58 57 50
|
||||
c
|
||||
Generated by Yosys
|
||||
11
tests/aiger/gold/_not_00000.aag
Normal file
11
tests/aiger/gold/_not_00000.aag
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
aag 6 6 0 2 0
|
||||
2
|
||||
4
|
||||
6
|
||||
8
|
||||
10
|
||||
12
|
||||
3
|
||||
5
|
||||
c
|
||||
Generated by Yosys
|
||||
11
tests/aiger/gold/_or_00000.aag
Normal file
11
tests/aiger/gold/_or_00000.aag
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
aag 6 4 0 2 2
|
||||
2
|
||||
4
|
||||
6
|
||||
8
|
||||
11
|
||||
13
|
||||
10 5 3
|
||||
12 7 3
|
||||
c
|
||||
Generated by Yosys
|
||||
9
tests/aiger/gold/_pos_00000.aag
Normal file
9
tests/aiger/gold/_pos_00000.aag
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
aag 1 1 0 5 0
|
||||
2
|
||||
2
|
||||
2
|
||||
2
|
||||
2
|
||||
2
|
||||
c
|
||||
Generated by Yosys
|
||||
7
tests/aiger/gold/_reduce_and_00000.aag
Normal file
7
tests/aiger/gold/_reduce_and_00000.aag
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
aag 1 1 0 3 0
|
||||
2
|
||||
2
|
||||
0
|
||||
0
|
||||
c
|
||||
Generated by Yosys
|
||||
13
tests/aiger/gold/_reduce_bool_00000.aag
Normal file
13
tests/aiger/gold/_reduce_bool_00000.aag
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
aag 7 4 0 3 3
|
||||
2
|
||||
4
|
||||
6
|
||||
8
|
||||
15
|
||||
0
|
||||
0
|
||||
10 5 3
|
||||
12 10 7
|
||||
14 12 9
|
||||
c
|
||||
Generated by Yosys
|
||||
7
tests/aiger/gold/_reduce_or_00000.aag
Normal file
7
tests/aiger/gold/_reduce_or_00000.aag
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
aag 3 2 0 1 1
|
||||
2
|
||||
4
|
||||
7
|
||||
6 5 3
|
||||
c
|
||||
Generated by Yosys
|
||||
30
tests/aiger/gold/_reduce_xnor_00000.aag
Normal file
30
tests/aiger/gold/_reduce_xnor_00000.aag
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
aag 25 6 0 2 19
|
||||
2
|
||||
4
|
||||
6
|
||||
8
|
||||
10
|
||||
12
|
||||
51
|
||||
0
|
||||
14 4 2
|
||||
16 5 3
|
||||
18 17 15
|
||||
20 18 6
|
||||
22 17 15
|
||||
24 23 7
|
||||
26 25 21
|
||||
28 26 8
|
||||
30 25 21
|
||||
32 31 9
|
||||
34 33 29
|
||||
36 34 10
|
||||
38 33 29
|
||||
40 39 11
|
||||
42 41 37
|
||||
44 42 12
|
||||
46 41 37
|
||||
48 47 13
|
||||
50 49 45
|
||||
c
|
||||
Generated by Yosys
|
||||
9
tests/aiger/gold/_reduce_xor_00000.aag
Normal file
9
tests/aiger/gold/_reduce_xor_00000.aag
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
aag 5 2 0 1 3
|
||||
2
|
||||
4
|
||||
10
|
||||
6 4 2
|
||||
8 5 3
|
||||
10 9 7
|
||||
c
|
||||
Generated by Yosys
|
||||
20
tests/aiger/gold/_sub_00000.aag
Normal file
20
tests/aiger/gold/_sub_00000.aag
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
aag 16 13 0 1 3
|
||||
2
|
||||
4
|
||||
6
|
||||
8
|
||||
10
|
||||
12
|
||||
14
|
||||
16
|
||||
18
|
||||
20
|
||||
22
|
||||
24
|
||||
26
|
||||
33
|
||||
28 17 2
|
||||
30 16 3
|
||||
32 31 29
|
||||
c
|
||||
Generated by Yosys
|
||||
17
tests/aiger/gold/_xnor_00000.aag
Normal file
17
tests/aiger/gold/_xnor_00000.aag
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
aag 10 4 0 4 6
|
||||
2
|
||||
4
|
||||
6
|
||||
8
|
||||
15
|
||||
21
|
||||
21
|
||||
21
|
||||
10 6 2
|
||||
12 7 3
|
||||
14 13 11
|
||||
16 8 4
|
||||
18 9 5
|
||||
20 19 17
|
||||
c
|
||||
Generated by Yosys
|
||||
12
tests/aiger/gold/_xor_00000.aag
Normal file
12
tests/aiger/gold/_xor_00000.aag
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
aag 8 5 0 1 3
|
||||
2
|
||||
4
|
||||
6
|
||||
8
|
||||
10
|
||||
16
|
||||
12 8 2
|
||||
14 9 3
|
||||
16 15 13
|
||||
c
|
||||
Generated by Yosys
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
|
||||
set -e
|
||||
|
||||
|
|
@ -57,3 +58,13 @@ for y in *.ys; do
|
|||
echo "Running $y."
|
||||
../../yosys -ql ${y%.*}.log $y
|
||||
done
|
||||
|
||||
# compare aigmap with reference
|
||||
# make gold with: rm gold/*; yosys --no-version -p "test_cell -aigmap -w gold/ -n 1 -s 1 all"
|
||||
rm -rf gate; mkdir gate
|
||||
../../yosys --no-version -p "test_cell -aigmap -w gate/ -n 1 -s 1 all"
|
||||
(
|
||||
set -o pipefail
|
||||
diff --brief gold gate | tee aigmap.err
|
||||
)
|
||||
rm aigmap.err
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
set -e
|
||||
for x in *.ys; do
|
||||
echo "Running $x.."
|
||||
|
|
|
|||
31
tests/arch/gowin/bug5688.ys
Normal file
31
tests/arch/gowin/bug5688.ys
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
read_verilog << EOT
|
||||
`default_nettype none
|
||||
|
||||
module top (
|
||||
input wire clk,
|
||||
input wire [9:0] rd_addr,
|
||||
output reg [15:0] rd_data,
|
||||
input wire [9:0] wr_addr,
|
||||
input wire [15:0] wr_data,
|
||||
input wire wr_en
|
||||
);
|
||||
|
||||
(* ram_style = "block" *) reg [15:0] mem [0:1023];
|
||||
|
||||
// Read port — separate always block
|
||||
always @(posedge clk) begin
|
||||
rd_data <= mem[rd_addr];
|
||||
end
|
||||
|
||||
// Write port — separate always block
|
||||
always @(posedge clk) begin
|
||||
if (wr_en)
|
||||
mem[wr_addr] <= wr_data;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
synth_gowin -top top
|
||||
splitnets
|
||||
select -assert-any top/mem.0.0 %ci*:+DPX9B[ADA]:+DFF:+IBUF i:wr_en %i
|
||||
53
tests/arch/gowin/mul_gw1n.ys
Normal file
53
tests/arch/gowin/mul_gw1n.ys
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
read_verilog ../common/mul.v
|
||||
chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
|
||||
hierarchy -top top
|
||||
proc
|
||||
# equivalence checking is somewhat slow (and missing simulation models)
|
||||
synth_gowin -family gw1n
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:MULT9X9
|
||||
|
||||
|
||||
# Make sure that DSPs are not inferred with -nodsp option
|
||||
design -reset
|
||||
read_verilog ../common/mul.v
|
||||
chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
|
||||
hierarchy -top top
|
||||
proc
|
||||
synth_gowin -family gw1n -nodsp
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-none t:MULT9X9
|
||||
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/mul.v
|
||||
chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32
|
||||
hierarchy -top top
|
||||
proc
|
||||
synth_gowin -family gw1n
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:MULT18X18
|
||||
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/mul.v
|
||||
chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64
|
||||
hierarchy -top top
|
||||
proc
|
||||
# equivalence checking is too slow here
|
||||
synth_gowin
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:MULT36X36
|
||||
|
||||
|
||||
# We end up with two 18x18 multipliers
|
||||
# 36x36 min width is 22
|
||||
design -reset
|
||||
read_verilog ../common/mul.v
|
||||
chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48
|
||||
hierarchy -top top
|
||||
proc
|
||||
# equivalence checking is too slow here
|
||||
synth_gowin
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 2 t:MULT18X18
|
||||
53
tests/arch/gowin/mul_gw2a.ys
Normal file
53
tests/arch/gowin/mul_gw2a.ys
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
read_verilog ../common/mul.v
|
||||
chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
|
||||
hierarchy -top top
|
||||
proc
|
||||
# equivalence checking is somewhat slow (and missing simulation models)
|
||||
synth_gowin -family gw2a
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:MULT9X9
|
||||
|
||||
|
||||
# Make sure that DSPs are not inferred with -nodsp option
|
||||
design -reset
|
||||
read_verilog ../common/mul.v
|
||||
chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
|
||||
hierarchy -top top
|
||||
proc
|
||||
synth_gowin -family gw2a -nodsp
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-none t:MULT9X9
|
||||
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/mul.v
|
||||
chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32
|
||||
hierarchy -top top
|
||||
proc
|
||||
synth_gowin -family gw2a
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:MULT18X18
|
||||
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/mul.v
|
||||
chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64
|
||||
hierarchy -top top
|
||||
proc
|
||||
# equivalence checking is too slow here
|
||||
synth_gowin -family gw2a
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:MULT36X36
|
||||
|
||||
|
||||
# We end up with two 18x18 multipliers
|
||||
# 36x36 min width is 22
|
||||
design -reset
|
||||
read_verilog ../common/mul.v
|
||||
chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48
|
||||
hierarchy -top top
|
||||
proc
|
||||
# equivalence checking is too slow here
|
||||
synth_gowin -family gw2a
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 2 t:MULT18X18
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
|
||||
set -e
|
||||
|
||||
|
|
|
|||
29
tests/arch/xilinx/dsp_preadder_sub.ys
Normal file
29
tests/arch/xilinx/dsp_preadder_sub.ys
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
read_verilog <<EOT
|
||||
module top(
|
||||
input signed [7:0] A,
|
||||
input signed [7:0] D,
|
||||
input signed [7:0] B,
|
||||
output signed [16:0] P
|
||||
);
|
||||
assign P = (A - D) * B;
|
||||
endmodule
|
||||
EOT
|
||||
|
||||
proc
|
||||
design -save gold
|
||||
synth_xilinx -noiopad
|
||||
design -save gate
|
||||
cd top
|
||||
select -assert-count 1 t:DSP48E1
|
||||
select -assert-count 1 t:DSP48E1 r:USE_DPORT=TRUE %i
|
||||
select -assert-none t:DSP48E1 %% t:* %D
|
||||
|
||||
# Now prove functional equivalence of the mapped netlist against the original
|
||||
# (saved as `gold` above).
|
||||
design -reset
|
||||
design -copy-from gold -as gold top
|
||||
design -copy-from gate -as gate top
|
||||
techmap -wb -D EQUIV -autoproc -map +/xilinx/cells_sim.v
|
||||
equiv_make gold gate equiv
|
||||
equiv_induct equiv
|
||||
equiv_status -assert equiv
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
|
||||
OPTIND=1
|
||||
seed="" # default to no seed specified
|
||||
|
|
|
|||
1
tests/blif/.gitignore
vendored
Normal file
1
tests/blif/.gitignore
vendored
Normal file
|
|
@ -0,0 +1 @@
|
|||
/*.out
|
||||
480
tests/blif/gatesi.blif
Normal file
480
tests/blif/gatesi.blif
Normal file
|
|
@ -0,0 +1,480 @@
|
|||
# Generated by Yosys 0.60+88 (git sha1 69b604104, g++ 15.2.1 -fPIC -O3)
|
||||
|
||||
.model test
|
||||
.inputs clk in_a_var[0] in_a_var[1] in_a_var[2] in_a_var[3] in_a_var[4] in_a_var[5] in_a_var[6] in_a_var[7] in_b_var[0] in_b_var[1] in_b_var[2] in_b_var[3] in_b_var[4] in_b_var[5] in_b_var[6] in_b_var[7]
|
||||
.outputs out_var[0] out_var[1] out_var[2] out_var[3] out_var[4] out_var[5] out_var[6] out_var[7]
|
||||
.gate ORNOT A=:1.test_1[0] B=in_a_var[0] Y=$abc$2385$new_n57
|
||||
.gate ORNOT A=in_a_var[0] B=:1.test_1[0] Y=$abc$2385$new_n58
|
||||
.gate XNOR A=:1.test_1[0] B=in_a_var[0] Y=$abc$2385$new_n59
|
||||
.gate NAND A=in_b_var[0] B=$abc$2385$new_n59 Y=$abc$2385$new_n60
|
||||
.gate XOR A=in_b_var[0] B=$abc$2385$new_n59 Y=$abc$2385$auto$maccmap.cc:114:fulladd$252.Y[0]
|
||||
.gate NAND A=$abc$2385$new_n57 B=$abc$2385$new_n60 Y=$abc$2385$new_n62
|
||||
.gate NOR A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n63
|
||||
.gate AND A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n64
|
||||
.gate XOR A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n65
|
||||
.gate NOT A=$abc$2385$new_n65 Y=$abc$2385$new_n66
|
||||
.gate AND A=:1.test_1[2] B=$abc$2385$new_n64 Y=$abc$2385$new_n67
|
||||
.gate AND A=:1.test_1[3] B=$abc$2385$new_n67 Y=$abc$2385$new_n68
|
||||
.gate AND A=:1.test_1[4] B=$abc$2385$new_n68 Y=$abc$2385$new_n69
|
||||
.gate AND A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n70
|
||||
.gate AND A=:1.test_1[6] B=$abc$2385$new_n70 Y=$abc$2385$new_n71
|
||||
.gate XNOR A=:1.test_1[6] B=$abc$2385$new_n70 Y=$abc$2385$new_n72
|
||||
.gate NOT A=$abc$2385$new_n72 Y=$abc$2385$new_n73
|
||||
.gate AND A=:1.test_1[7] B=$abc$2385$new_n71 Y=$abc$2385$new_n74
|
||||
.gate XNOR A=:1.test_1[7] B=$abc$2385$new_n71 Y=$abc$2385$new_n75
|
||||
.gate ANDNOT A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n76
|
||||
.gate XNOR A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n77
|
||||
.gate NOR A=:1.test_1[3] B=:1.test_1[4] Y=$abc$2385$new_n78
|
||||
.gate AND A=$abc$2385$new_n63 B=$abc$2385$new_n78 Y=$abc$2385$new_n79
|
||||
.gate ANDNOT A=$abc$2385$new_n79 B=:1.test_1[2] Y=$abc$2385$new_n80
|
||||
.gate AND A=$abc$2385$new_n77 B=$abc$2385$new_n80 Y=$abc$2385$new_n81
|
||||
.gate NAND A=$abc$2385$new_n75 B=$abc$2385$new_n81 Y=$abc$2385$new_n82
|
||||
.gate OR A=$abc$2385$new_n73 B=$abc$2385$new_n82 Y=$abc$2385$new_n83
|
||||
.gate AND A=$abc$2385$new_n66 B=$abc$2385$new_n83 Y=$abc$2385$new_n84
|
||||
.gate ORNOT A=$abc$2385$new_n84 B=in_a_var[1] Y=$abc$2385$new_n85
|
||||
.gate XNOR A=in_a_var[1] B=$abc$2385$new_n84 Y=$abc$2385$new_n86
|
||||
.gate NAND A=in_b_var[1] B=$abc$2385$new_n86 Y=$abc$2385$new_n87
|
||||
.gate XNOR A=in_b_var[1] B=$abc$2385$new_n86 Y=$abc$2385$new_n88
|
||||
.gate ANDNOT A=$abc$2385$new_n62 B=$abc$2385$new_n88 Y=$abc$2385$new_n89
|
||||
.gate AND A=$abc$2385$new_n85 B=$abc$2385$new_n87 Y=$abc$2385$new_n90
|
||||
.gate XNOR A=:1.test_1[2] B=$abc$2385$new_n64 Y=$abc$2385$new_n91
|
||||
.gate AND A=$abc$2385$new_n83 B=$abc$2385$new_n91 Y=$abc$2385$new_n92
|
||||
.gate ORNOT A=$abc$2385$new_n92 B=in_a_var[2] Y=$abc$2385$new_n93
|
||||
.gate XNOR A=in_a_var[2] B=$abc$2385$new_n92 Y=$abc$2385$new_n94
|
||||
.gate NAND A=in_b_var[2] B=$abc$2385$new_n94 Y=$abc$2385$new_n95
|
||||
.gate XNOR A=in_b_var[2] B=$abc$2385$new_n94 Y=$abc$2385$new_n96
|
||||
.gate OR A=$abc$2385$new_n90 B=$abc$2385$new_n96 Y=$abc$2385$new_n97
|
||||
.gate XOR A=$abc$2385$new_n90 B=$abc$2385$new_n96 Y=$abc$2385$new_n98
|
||||
.gate NAND A=$abc$2385$new_n89 B=$abc$2385$new_n98 Y=$abc$2385$new_n99
|
||||
.gate XOR A=$abc$2385$new_n89 B=$abc$2385$new_n98 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[2]
|
||||
.gate NAND A=$abc$2385$new_n97 B=$abc$2385$new_n99 Y=$abc$2385$new_n101
|
||||
.gate AND A=$abc$2385$new_n93 B=$abc$2385$new_n95 Y=$abc$2385$new_n102
|
||||
.gate XNOR A=:1.test_1[3] B=$abc$2385$new_n67 Y=$abc$2385$new_n103
|
||||
.gate AND A=$abc$2385$new_n83 B=$abc$2385$new_n103 Y=$abc$2385$new_n104
|
||||
.gate ORNOT A=$abc$2385$new_n104 B=in_a_var[3] Y=$abc$2385$new_n105
|
||||
.gate XNOR A=in_a_var[3] B=$abc$2385$new_n104 Y=$abc$2385$new_n106
|
||||
.gate NAND A=in_b_var[3] B=$abc$2385$new_n106 Y=$abc$2385$new_n107
|
||||
.gate XNOR A=in_b_var[3] B=$abc$2385$new_n106 Y=$abc$2385$new_n108
|
||||
.gate OR A=$abc$2385$new_n102 B=$abc$2385$new_n108 Y=$abc$2385$new_n109
|
||||
.gate XOR A=$abc$2385$new_n102 B=$abc$2385$new_n108 Y=$abc$2385$new_n110
|
||||
.gate NAND A=$abc$2385$new_n101 B=$abc$2385$new_n110 Y=$abc$2385$new_n111
|
||||
.gate XOR A=$abc$2385$new_n101 B=$abc$2385$new_n110 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[3]
|
||||
.gate NAND A=$abc$2385$new_n109 B=$abc$2385$new_n111 Y=$abc$2385$new_n113
|
||||
.gate AND A=$abc$2385$new_n105 B=$abc$2385$new_n107 Y=$abc$2385$new_n114
|
||||
.gate XNOR A=:1.test_1[4] B=$abc$2385$new_n68 Y=$abc$2385$new_n115
|
||||
.gate AND A=$abc$2385$new_n83 B=$abc$2385$new_n115 Y=$abc$2385$new_n116
|
||||
.gate ORNOT A=$abc$2385$new_n116 B=in_a_var[4] Y=$abc$2385$new_n117
|
||||
.gate XNOR A=in_a_var[4] B=$abc$2385$new_n116 Y=$abc$2385$new_n118
|
||||
.gate NAND A=in_b_var[4] B=$abc$2385$new_n118 Y=$abc$2385$new_n119
|
||||
.gate XNOR A=in_b_var[4] B=$abc$2385$new_n118 Y=$abc$2385$new_n120
|
||||
.gate OR A=$abc$2385$new_n114 B=$abc$2385$new_n120 Y=$abc$2385$new_n121
|
||||
.gate XOR A=$abc$2385$new_n114 B=$abc$2385$new_n120 Y=$abc$2385$new_n122
|
||||
.gate NAND A=$abc$2385$new_n113 B=$abc$2385$new_n122 Y=$abc$2385$new_n123
|
||||
.gate XOR A=$abc$2385$new_n113 B=$abc$2385$new_n122 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[4]
|
||||
.gate AND A=$abc$2385$new_n121 B=$abc$2385$new_n123 Y=$abc$2385$new_n125
|
||||
.gate AND A=$abc$2385$new_n117 B=$abc$2385$new_n119 Y=$abc$2385$new_n126
|
||||
.gate AND A=$abc$2385$new_n77 B=$abc$2385$new_n83 Y=$abc$2385$new_n127
|
||||
.gate ORNOT A=$abc$2385$new_n127 B=in_a_var[5] Y=$abc$2385$new_n128
|
||||
.gate XNOR A=in_a_var[5] B=$abc$2385$new_n127 Y=$abc$2385$new_n129
|
||||
.gate NAND A=in_b_var[5] B=$abc$2385$new_n129 Y=$abc$2385$new_n130
|
||||
.gate XNOR A=in_b_var[5] B=$abc$2385$new_n129 Y=$abc$2385$new_n131
|
||||
.gate OR A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n132
|
||||
.gate NAND A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n133
|
||||
.gate XOR A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n134
|
||||
.gate XNOR A=$abc$2385$new_n125 B=$abc$2385$new_n134 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[5]
|
||||
.gate AND A=$abc$2385$new_n128 B=$abc$2385$new_n130 Y=$abc$2385$new_n136
|
||||
.gate AND A=$abc$2385$new_n72 B=$abc$2385$new_n82 Y=$abc$2385$new_n137
|
||||
.gate ORNOT A=$abc$2385$new_n137 B=in_a_var[6] Y=$abc$2385$new_n138
|
||||
.gate XNOR A=in_a_var[6] B=$abc$2385$new_n137 Y=$abc$2385$new_n139
|
||||
.gate NAND A=in_b_var[6] B=$abc$2385$new_n139 Y=$abc$2385$new_n140
|
||||
.gate XNOR A=in_b_var[6] B=$abc$2385$new_n139 Y=$abc$2385$new_n141
|
||||
.gate OR A=$abc$2385$new_n136 B=$abc$2385$new_n141 Y=$abc$2385$new_n142
|
||||
.gate XOR A=$abc$2385$new_n136 B=$abc$2385$new_n141 Y=$abc$2385$new_n143
|
||||
.gate NAND A=$abc$2385$new_n125 B=$abc$2385$new_n132 Y=$abc$2385$new_n144
|
||||
.gate AND A=$abc$2385$new_n133 B=$abc$2385$new_n144 Y=$abc$2385$new_n145
|
||||
.gate NAND A=$abc$2385$new_n143 B=$abc$2385$new_n145 Y=$abc$2385$new_n146
|
||||
.gate XOR A=$abc$2385$new_n143 B=$abc$2385$new_n145 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[6]
|
||||
.gate AND A=$abc$2385$new_n142 B=$abc$2385$new_n146 Y=$abc$2385$new_n148
|
||||
.gate AND A=$abc$2385$new_n138 B=$abc$2385$new_n140 Y=$abc$2385$new_n149
|
||||
.gate AND A=$abc$2385$new_n75 B=$abc$2385$new_n83 Y=$abc$2385$new_n150
|
||||
.gate NOR A=in_b_var[7] B=in_a_var[7] Y=$abc$2385$new_n151
|
||||
.gate XOR A=in_b_var[7] B=in_a_var[7] Y=$abc$2385$new_n152
|
||||
.gate XNOR A=$abc$2385$new_n150 B=$abc$2385$new_n152 Y=$abc$2385$new_n153
|
||||
.gate XNOR A=$abc$2385$new_n149 B=$abc$2385$new_n153 Y=$abc$2385$new_n154
|
||||
.gate XNOR A=$abc$2385$new_n148 B=$abc$2385$new_n154 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[7]
|
||||
.gate XNOR A=$abc$2385$new_n62 B=$abc$2385$new_n88 Y=$abc$2385$auto$maccmap.cc:240:synth$253.P[1]
|
||||
.gate NAND A=:1.test_1[0] B=:1.test_2[0] Y=$abc$2385$new_n157
|
||||
.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n91 Y=$abc$2385$new_n158
|
||||
.gate ANDNOT A=:1.test_2[1] B=$abc$2385$new_n64 Y=$abc$2385$new_n159
|
||||
.gate AND A=:1.test_2[1] B=$abc$2385$new_n65 Y=$abc$2385$new_n160
|
||||
.gate ORNOT A=$abc$2385$new_n160 B=:1.test_1[0] Y=$abc$2385$new_n161
|
||||
.gate AND A=:1.test_2[2] B=$abc$2385$new_n161 Y=$abc$2385$new_n162
|
||||
.gate ANDNOT A=:1.test_1[1] B=:1.test_1[0] Y=$abc$2385$new_n163
|
||||
.gate ANDNOT A=:1.test_2[2] B=:1.test_1[0] Y=$abc$2385$new_n164
|
||||
.gate XNOR A=$abc$2385$new_n160 B=$abc$2385$new_n164 Y=$abc$2385$new_n165
|
||||
.gate MUX A=$abc$2385$new_n160 B=$abc$2385$new_n165 S=:1.test_2[2] Y=$abc$2385$new_n166
|
||||
.gate ORNOT A=:1.test_2[0] B=:1.test_1[0] Y=$abc$2385$new_n167
|
||||
.gate AND A=$abc$2385$new_n159 B=$abc$2385$new_n167 Y=$abc$2385$new_n168
|
||||
.gate AND A=$abc$2385$new_n166 B=$abc$2385$new_n168 Y=$abc$2385$new_n169
|
||||
.gate XOR A=$abc$2385$new_n166 B=$abc$2385$new_n168 Y=$abc$2385$new_n170
|
||||
.gate AND A=$abc$2385$new_n158 B=$abc$2385$new_n170 Y=$abc$2385$new_n171
|
||||
.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n103 Y=$abc$2385$new_n172
|
||||
.gate ANDNOT A=:1.test_2[1] B=$abc$2385$new_n91 Y=$abc$2385$new_n173
|
||||
.gate ANDNOT A=:1.test_2[1] B=$abc$2385$new_n103 Y=$abc$2385$new_n174
|
||||
.gate AND A=$abc$2385$new_n158 B=$abc$2385$new_n174 Y=$abc$2385$new_n175
|
||||
.gate XOR A=$abc$2385$new_n172 B=$abc$2385$new_n173 Y=$abc$2385$new_n176
|
||||
.gate NAND A=:1.test_2[2] B=$abc$2385$new_n65 Y=$abc$2385$new_n177
|
||||
.gate AND A=:1.test_1[0] B=:1.test_2[3] Y=$abc$2385$new_n178
|
||||
.gate NAND A=:1.test_1[0] B=$abc$2385$new_n177 Y=$abc$2385$new_n179
|
||||
.gate XNOR A=$abc$2385$new_n177 B=$abc$2385$new_n178 Y=$abc$2385$new_n180
|
||||
.gate NAND A=$abc$2385$new_n162 B=$abc$2385$new_n180 Y=$abc$2385$new_n181
|
||||
.gate XOR A=$abc$2385$new_n162 B=$abc$2385$new_n180 Y=$abc$2385$new_n182
|
||||
.gate NAND A=$abc$2385$new_n176 B=$abc$2385$new_n182 Y=$abc$2385$new_n183
|
||||
.gate XOR A=$abc$2385$new_n176 B=$abc$2385$new_n182 Y=$abc$2385$new_n184
|
||||
.gate NAND A=$abc$2385$new_n171 B=$abc$2385$new_n184 Y=$abc$2385$new_n185
|
||||
.gate XOR A=$abc$2385$new_n171 B=$abc$2385$new_n184 Y=$abc$2385$new_n186
|
||||
.gate NAND A=$abc$2385$new_n169 B=$abc$2385$new_n186 Y=$abc$2385$new_n187
|
||||
.gate NAND A=$abc$2385$new_n185 B=$abc$2385$new_n187 Y=$abc$2385$new_n188
|
||||
.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n115 Y=$abc$2385$new_n189
|
||||
.gate ANDNOT A=:1.test_2[1] B=$abc$2385$new_n115 Y=$abc$2385$new_n190
|
||||
.gate NAND A=$abc$2385$new_n172 B=$abc$2385$new_n190 Y=$abc$2385$new_n191
|
||||
.gate XOR A=$abc$2385$new_n174 B=$abc$2385$new_n189 Y=$abc$2385$new_n192
|
||||
.gate ANDNOT A=:1.test_2[2] B=$abc$2385$new_n91 Y=$abc$2385$new_n193
|
||||
.gate NAND A=$abc$2385$new_n192 B=$abc$2385$new_n193 Y=$abc$2385$new_n194
|
||||
.gate XOR A=$abc$2385$new_n192 B=$abc$2385$new_n193 Y=$abc$2385$new_n195
|
||||
.gate AND A=:1.test_2[3] B=$abc$2385$new_n179 Y=$abc$2385$new_n196
|
||||
.gate NAND A=:1.test_2[3] B=$abc$2385$new_n65 Y=$abc$2385$new_n197
|
||||
.gate NAND A=:1.test_1[0] B=$abc$2385$new_n197 Y=$abc$2385$new_n198
|
||||
.gate AND A=:1.test_2[4] B=$abc$2385$new_n198 Y=$abc$2385$new_n199
|
||||
.gate NAND A=:1.test_2[3] B=$abc$2385$new_n163 Y=$abc$2385$new_n200
|
||||
.gate NAND A=$abc$2385$new_n199 B=$abc$2385$new_n200 Y=$abc$2385$new_n201
|
||||
.gate ORNOT A=:1.test_2[4] B=$abc$2385$new_n197 Y=$abc$2385$new_n202
|
||||
.gate AND A=$abc$2385$new_n201 B=$abc$2385$new_n202 Y=$abc$2385$new_n203
|
||||
.gate NAND A=$abc$2385$new_n175 B=$abc$2385$new_n203 Y=$abc$2385$new_n204
|
||||
.gate XOR A=$abc$2385$new_n175 B=$abc$2385$new_n203 Y=$abc$2385$new_n205
|
||||
.gate NAND A=$abc$2385$new_n196 B=$abc$2385$new_n205 Y=$abc$2385$new_n206
|
||||
.gate XOR A=$abc$2385$new_n196 B=$abc$2385$new_n205 Y=$abc$2385$new_n207
|
||||
.gate AND A=$abc$2385$new_n195 B=$abc$2385$new_n207 Y=$abc$2385$new_n208
|
||||
.gate XOR A=$abc$2385$new_n195 B=$abc$2385$new_n207 Y=$abc$2385$new_n209
|
||||
.gate NAND A=$abc$2385$new_n181 B=$abc$2385$new_n183 Y=$abc$2385$new_n210
|
||||
.gate AND A=$abc$2385$new_n209 B=$abc$2385$new_n210 Y=$abc$2385$new_n211
|
||||
.gate XOR A=$abc$2385$new_n209 B=$abc$2385$new_n210 Y=$abc$2385$new_n212
|
||||
.gate AND A=$abc$2385$new_n188 B=$abc$2385$new_n212 Y=$abc$2385$new_n213
|
||||
.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n77 Y=$abc$2385$new_n214
|
||||
.gate ANDNOT A=:1.test_2[3] B=$abc$2385$new_n91 Y=$abc$2385$new_n215
|
||||
.gate ANDNOT A=:1.test_2[2] B=$abc$2385$new_n103 Y=$abc$2385$new_n216
|
||||
.gate ANDNOT A=:1.test_2[2] B=$abc$2385$new_n115 Y=$abc$2385$new_n217
|
||||
.gate NAND A=$abc$2385$new_n174 B=$abc$2385$new_n217 Y=$abc$2385$new_n218
|
||||
.gate XOR A=$abc$2385$new_n190 B=$abc$2385$new_n216 Y=$abc$2385$new_n219
|
||||
.gate NAND A=$abc$2385$new_n215 B=$abc$2385$new_n219 Y=$abc$2385$new_n220
|
||||
.gate XOR A=$abc$2385$new_n215 B=$abc$2385$new_n219 Y=$abc$2385$new_n221
|
||||
.gate AND A=$abc$2385$new_n214 B=$abc$2385$new_n221 Y=$abc$2385$new_n222
|
||||
.gate XOR A=$abc$2385$new_n214 B=$abc$2385$new_n221 Y=$abc$2385$new_n223
|
||||
.gate NAND A=:1.test_2[4] B=$abc$2385$new_n65 Y=$abc$2385$new_n224
|
||||
.gate NAND A=:1.test_1[0] B=$abc$2385$new_n224 Y=$abc$2385$new_n225
|
||||
.gate AND A=:1.test_2[5] B=$abc$2385$new_n225 Y=$abc$2385$new_n226
|
||||
.gate NAND A=:1.test_2[4] B=$abc$2385$new_n163 Y=$abc$2385$new_n227
|
||||
.gate NAND A=$abc$2385$new_n226 B=$abc$2385$new_n227 Y=$abc$2385$new_n228
|
||||
.gate ORNOT A=:1.test_2[5] B=$abc$2385$new_n224 Y=$abc$2385$new_n229
|
||||
.gate AND A=$abc$2385$new_n228 B=$abc$2385$new_n229 Y=$abc$2385$new_n230
|
||||
.gate NAND A=$abc$2385$new_n191 B=$abc$2385$new_n194 Y=$abc$2385$new_n231
|
||||
.gate NAND A=$abc$2385$new_n230 B=$abc$2385$new_n231 Y=$abc$2385$new_n232
|
||||
.gate XOR A=$abc$2385$new_n230 B=$abc$2385$new_n231 Y=$abc$2385$new_n233
|
||||
.gate NAND A=$abc$2385$new_n199 B=$abc$2385$new_n233 Y=$abc$2385$new_n234
|
||||
.gate XOR A=$abc$2385$new_n199 B=$abc$2385$new_n233 Y=$abc$2385$new_n235
|
||||
.gate AND A=$abc$2385$new_n223 B=$abc$2385$new_n235 Y=$abc$2385$new_n236
|
||||
.gate XOR A=$abc$2385$new_n223 B=$abc$2385$new_n235 Y=$abc$2385$new_n237
|
||||
.gate NAND A=$abc$2385$new_n208 B=$abc$2385$new_n237 Y=$abc$2385$new_n238
|
||||
.gate XOR A=$abc$2385$new_n208 B=$abc$2385$new_n237 Y=$abc$2385$new_n239
|
||||
.gate NAND A=$abc$2385$new_n204 B=$abc$2385$new_n206 Y=$abc$2385$new_n240
|
||||
.gate NAND A=$abc$2385$new_n239 B=$abc$2385$new_n240 Y=$abc$2385$new_n241
|
||||
.gate XOR A=$abc$2385$new_n239 B=$abc$2385$new_n240 Y=$abc$2385$new_n242
|
||||
.gate AND A=$abc$2385$new_n211 B=$abc$2385$new_n242 Y=$abc$2385$new_n243
|
||||
.gate XOR A=$abc$2385$new_n211 B=$abc$2385$new_n242 Y=$abc$2385$new_n244
|
||||
.gate NAND A=$abc$2385$new_n213 B=$abc$2385$new_n244 Y=$abc$2385$new_n245
|
||||
.gate AND A=:1.test_2[0] B=$abc$2385$new_n163 Y=$abc$2385$new_n246
|
||||
.gate NAND A=:1.test_2[0] B=$abc$2385$new_n163 Y=$abc$2385$new_n247
|
||||
.gate XOR A=$abc$2385$new_n158 B=$abc$2385$new_n170 Y=$abc$2385$new_n248
|
||||
.gate AND A=$abc$2385$new_n246 B=$abc$2385$new_n248 Y=$abc$2385$new_n249
|
||||
.gate XOR A=$abc$2385$new_n169 B=$abc$2385$new_n186 Y=$abc$2385$new_n250
|
||||
.gate AND A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n251
|
||||
.gate XOR A=$abc$2385$new_n188 B=$abc$2385$new_n212 Y=$abc$2385$new_n252
|
||||
.gate AND A=$abc$2385$new_n251 B=$abc$2385$new_n252 Y=$abc$2385$new_n253
|
||||
.gate NAND A=$abc$2385$new_n244 B=$abc$2385$new_n253 Y=$abc$2385$new_n254
|
||||
.gate XNOR A=$abc$2385$new_n213 B=$abc$2385$new_n244 Y=$abc$2385$new_n255
|
||||
.gate NAND A=$abc$2385$new_n245 B=$abc$2385$new_n254 Y=$abc$2385$new_n256
|
||||
.gate NAND A=$abc$2385$new_n238 B=$abc$2385$new_n241 Y=$abc$2385$new_n257
|
||||
.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n72 Y=$abc$2385$new_n258
|
||||
.gate ORNOT A=$abc$2385$new_n77 B=:1.test_2[1] Y=$abc$2385$new_n259
|
||||
.gate ANDNOT A=:1.test_2[1] B=$abc$2385$new_n72 Y=$abc$2385$new_n260
|
||||
.gate NAND A=$abc$2385$new_n214 B=$abc$2385$new_n260 Y=$abc$2385$new_n261
|
||||
.gate XNOR A=$abc$2385$new_n258 B=$abc$2385$new_n259 Y=$abc$2385$new_n262
|
||||
.gate ANDNOT A=:1.test_2[4] B=$abc$2385$new_n91 Y=$abc$2385$new_n263
|
||||
.gate ANDNOT A=:1.test_2[3] B=$abc$2385$new_n103 Y=$abc$2385$new_n264
|
||||
.gate ANDNOT A=:1.test_2[3] B=$abc$2385$new_n115 Y=$abc$2385$new_n265
|
||||
.gate NAND A=$abc$2385$new_n216 B=$abc$2385$new_n265 Y=$abc$2385$new_n266
|
||||
.gate XOR A=$abc$2385$new_n217 B=$abc$2385$new_n264 Y=$abc$2385$new_n267
|
||||
.gate NAND A=$abc$2385$new_n263 B=$abc$2385$new_n267 Y=$abc$2385$new_n268
|
||||
.gate XOR A=$abc$2385$new_n263 B=$abc$2385$new_n267 Y=$abc$2385$new_n269
|
||||
.gate AND A=$abc$2385$new_n262 B=$abc$2385$new_n269 Y=$abc$2385$new_n270
|
||||
.gate XOR A=$abc$2385$new_n262 B=$abc$2385$new_n269 Y=$abc$2385$new_n271
|
||||
.gate NAND A=$abc$2385$new_n222 B=$abc$2385$new_n271 Y=$abc$2385$new_n272
|
||||
.gate XOR A=$abc$2385$new_n222 B=$abc$2385$new_n271 Y=$abc$2385$new_n273
|
||||
.gate NAND A=:1.test_2[5] B=$abc$2385$new_n65 Y=$abc$2385$new_n274
|
||||
.gate NAND A=:1.test_1[0] B=$abc$2385$new_n274 Y=$abc$2385$new_n275
|
||||
.gate AND A=:1.test_2[6] B=$abc$2385$new_n275 Y=$abc$2385$new_n276
|
||||
.gate NAND A=:1.test_2[5] B=$abc$2385$new_n163 Y=$abc$2385$new_n277
|
||||
.gate NAND A=:1.test_2[6] B=$abc$2385$new_n65 Y=$abc$2385$new_n278
|
||||
.gate NAND A=$abc$2385$new_n276 B=$abc$2385$new_n277 Y=$abc$2385$new_n279
|
||||
.gate ORNOT A=:1.test_2[6] B=$abc$2385$new_n274 Y=$abc$2385$new_n280
|
||||
.gate AND A=$abc$2385$new_n279 B=$abc$2385$new_n280 Y=$abc$2385$new_n281
|
||||
.gate NAND A=$abc$2385$new_n218 B=$abc$2385$new_n220 Y=$abc$2385$new_n282
|
||||
.gate NAND A=$abc$2385$new_n281 B=$abc$2385$new_n282 Y=$abc$2385$new_n283
|
||||
.gate XOR A=$abc$2385$new_n281 B=$abc$2385$new_n282 Y=$abc$2385$new_n284
|
||||
.gate NAND A=$abc$2385$new_n226 B=$abc$2385$new_n284 Y=$abc$2385$new_n285
|
||||
.gate XOR A=$abc$2385$new_n226 B=$abc$2385$new_n284 Y=$abc$2385$new_n286
|
||||
.gate NAND A=$abc$2385$new_n273 B=$abc$2385$new_n286 Y=$abc$2385$new_n287
|
||||
.gate XOR A=$abc$2385$new_n273 B=$abc$2385$new_n286 Y=$abc$2385$new_n288
|
||||
.gate NAND A=$abc$2385$new_n236 B=$abc$2385$new_n288 Y=$abc$2385$new_n289
|
||||
.gate XOR A=$abc$2385$new_n236 B=$abc$2385$new_n288 Y=$abc$2385$new_n290
|
||||
.gate NAND A=$abc$2385$new_n232 B=$abc$2385$new_n234 Y=$abc$2385$new_n291
|
||||
.gate NAND A=$abc$2385$new_n290 B=$abc$2385$new_n291 Y=$abc$2385$new_n292
|
||||
.gate XOR A=$abc$2385$new_n290 B=$abc$2385$new_n291 Y=$abc$2385$new_n293
|
||||
.gate NAND A=$abc$2385$new_n257 B=$abc$2385$new_n293 Y=$abc$2385$new_n294
|
||||
.gate XOR A=$abc$2385$new_n257 B=$abc$2385$new_n293 Y=$abc$2385$new_n295
|
||||
.gate NAND A=$abc$2385$new_n243 B=$abc$2385$new_n295 Y=$abc$2385$new_n296
|
||||
.gate XOR A=$abc$2385$new_n243 B=$abc$2385$new_n295 Y=$abc$2385$new_n297
|
||||
.gate NAND A=$abc$2385$new_n256 B=$abc$2385$new_n297 Y=$abc$2385$new_n298
|
||||
.gate XNOR A=$abc$2385$new_n256 B=$abc$2385$new_n297 Y=$abc$2385$new_n299
|
||||
.gate NAND A=$abc$2385$new_n73 B=$abc$2385$new_n299 Y=$abc$2385$new_n300
|
||||
.gate OR A=$abc$2385$new_n73 B=$abc$2385$new_n299 Y=$abc$2385$new_n301
|
||||
.gate XOR A=$abc$2385$new_n253 B=$abc$2385$new_n255 Y=$abc$2385$new_n302
|
||||
.gate XNOR A=$abc$2385$new_n251 B=$abc$2385$new_n252 Y=$abc$2385$new_n303
|
||||
.gate XOR A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n304
|
||||
.gate XNOR A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n305
|
||||
.gate NAND A=$abc$2385$new_n103 B=$abc$2385$new_n304 Y=$abc$2385$new_n306
|
||||
.gate OR A=$abc$2385$new_n103 B=$abc$2385$new_n304 Y=$abc$2385$new_n307
|
||||
.gate XNOR A=$abc$2385$new_n247 B=$abc$2385$new_n248 Y=$abc$2385$new_n308
|
||||
.gate NAND A=:1.test_1[0] B=:1.test_2[1] Y=$abc$2385$new_n309
|
||||
.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n64 Y=$abc$2385$new_n310
|
||||
.gate XNOR A=$abc$2385$new_n309 B=$abc$2385$new_n310 Y=$abc$2385$new_n311
|
||||
.gate NAND A=$abc$2385$new_n66 B=$abc$2385$new_n311 Y=$abc$2385$new_n312
|
||||
.gate OR A=:1.test_2[1] B=$abc$2385$new_n157 Y=$abc$2385$new_n313
|
||||
.gate NAND A=$abc$2385$new_n312 B=$abc$2385$new_n313 Y=$abc$2385$new_n314
|
||||
.gate OR A=$abc$2385$new_n308 B=$abc$2385$new_n314 Y=$abc$2385$new_n315
|
||||
.gate NAND A=$abc$2385$new_n91 B=$abc$2385$new_n315 Y=$abc$2385$new_n316
|
||||
.gate NAND A=$abc$2385$new_n308 B=$abc$2385$new_n314 Y=$abc$2385$new_n317
|
||||
.gate NAND A=$abc$2385$new_n316 B=$abc$2385$new_n317 Y=$abc$2385$new_n318
|
||||
.gate NAND A=$abc$2385$new_n307 B=$abc$2385$new_n318 Y=$abc$2385$new_n319
|
||||
.gate NAND A=$abc$2385$new_n247 B=$abc$2385$new_n311 Y=$abc$2385$new_n320
|
||||
.gate NAND A=$abc$2385$new_n306 B=$abc$2385$new_n319 Y=$abc$2385$new_n321
|
||||
.gate ORNOT A=$abc$2385$new_n115 B=$abc$2385$new_n303 Y=$abc$2385$new_n322
|
||||
.gate ORNOT A=$abc$2385$new_n303 B=$abc$2385$new_n115 Y=$abc$2385$new_n323
|
||||
.gate NAND A=$abc$2385$new_n321 B=$abc$2385$new_n322 Y=$abc$2385$new_n324
|
||||
.gate NAND A=$abc$2385$new_n323 B=$abc$2385$new_n324 Y=$abc$2385$new_n325
|
||||
.gate NAND A=$abc$2385$new_n77 B=$abc$2385$new_n325 Y=$abc$2385$new_n326
|
||||
.gate NAND A=$abc$2385$new_n302 B=$abc$2385$new_n326 Y=$abc$2385$new_n327
|
||||
.gate OR A=$abc$2385$new_n77 B=$abc$2385$new_n325 Y=$abc$2385$new_n328
|
||||
.gate AND A=$abc$2385$new_n327 B=$abc$2385$new_n328 Y=$abc$2385$new_n329
|
||||
.gate NAND A=$abc$2385$new_n300 B=$abc$2385$new_n329 Y=$abc$2385$new_n330
|
||||
.gate AND A=$abc$2385$new_n301 B=$abc$2385$new_n330 Y=$abc$2385$new_n331
|
||||
.gate NAND A=$abc$2385$new_n75 B=$abc$2385$new_n331 Y=$abc$2385$new_n332
|
||||
.gate OR A=in_b_var[5] B=$abc$2385$new_n302 Y=$abc$2385$new_n333
|
||||
.gate NAND A=in_b_var[4] B=$abc$2385$new_n303 Y=$abc$2385$new_n334
|
||||
.gate OR A=in_b_var[4] B=$abc$2385$new_n303 Y=$abc$2385$new_n335
|
||||
.gate AND A=in_b_var[1] B=$abc$2385$new_n320 Y=$abc$2385$new_n336
|
||||
.gate OR A=in_b_var[3] B=$abc$2385$new_n305 Y=$abc$2385$new_n337
|
||||
.gate ANDNOT A=in_b_var[2] B=$abc$2385$new_n308 Y=$abc$2385$new_n338
|
||||
.gate XNOR A=in_b_var[2] B=$abc$2385$new_n308 Y=$abc$2385$new_n339
|
||||
.gate NAND A=in_b_var[3] B=$abc$2385$new_n305 Y=$abc$2385$new_n340
|
||||
.gate XNOR A=in_b_var[3] B=$abc$2385$new_n304 Y=$abc$2385$new_n341
|
||||
.gate AND A=$abc$2385$new_n339 B=$abc$2385$new_n341 Y=$abc$2385$new_n342
|
||||
.gate NAND A=$abc$2385$new_n336 B=$abc$2385$new_n342 Y=$abc$2385$new_n343
|
||||
.gate NAND A=$abc$2385$new_n337 B=$abc$2385$new_n338 Y=$abc$2385$new_n344
|
||||
.gate AND A=$abc$2385$new_n340 B=$abc$2385$new_n344 Y=$abc$2385$new_n345
|
||||
.gate AND A=$abc$2385$new_n343 B=$abc$2385$new_n345 Y=$abc$2385$new_n346
|
||||
.gate AND A=in_b_var[0] B=$abc$2385$new_n157 Y=$abc$2385$new_n347
|
||||
.gate XOR A=in_b_var[1] B=$abc$2385$new_n320 Y=$abc$2385$new_n348
|
||||
.gate AND A=$abc$2385$new_n342 B=$abc$2385$new_n348 Y=$abc$2385$new_n349
|
||||
.gate NAND A=$abc$2385$new_n347 B=$abc$2385$new_n349 Y=$abc$2385$new_n350
|
||||
.gate NAND A=$abc$2385$new_n346 B=$abc$2385$new_n350 Y=$abc$2385$new_n351
|
||||
.gate NAND A=$abc$2385$new_n335 B=$abc$2385$new_n351 Y=$abc$2385$new_n352
|
||||
.gate NAND A=$abc$2385$new_n334 B=$abc$2385$new_n352 Y=$abc$2385$new_n353
|
||||
.gate NAND A=$abc$2385$new_n333 B=$abc$2385$new_n353 Y=$abc$2385$new_n354
|
||||
.gate NAND A=in_b_var[6] B=$abc$2385$new_n299 Y=$abc$2385$new_n355
|
||||
.gate NAND A=in_b_var[5] B=$abc$2385$new_n302 Y=$abc$2385$new_n356
|
||||
.gate AND A=$abc$2385$new_n355 B=$abc$2385$new_n356 Y=$abc$2385$new_n357
|
||||
.gate NAND A=$abc$2385$new_n354 B=$abc$2385$new_n357 Y=$abc$2385$new_n358
|
||||
.gate AND A=$abc$2385$new_n157 B=$abc$2385$new_n320 Y=$abc$2385$new_n359
|
||||
.gate ANDNOT A=$abc$2385$new_n359 B=$abc$2385$new_n308 Y=$abc$2385$new_n360
|
||||
.gate AND A=$abc$2385$new_n305 B=$abc$2385$new_n360 Y=$abc$2385$new_n361
|
||||
.gate AND A=$abc$2385$new_n303 B=$abc$2385$new_n361 Y=$abc$2385$new_n362
|
||||
.gate AND A=$abc$2385$new_n302 B=$abc$2385$new_n362 Y=$abc$2385$new_n363
|
||||
.gate NAND A=$abc$2385$new_n299 B=$abc$2385$new_n363 Y=$abc$2385$new_n364
|
||||
.gate AND A=$abc$2385$new_n296 B=$abc$2385$new_n298 Y=$abc$2385$new_n365
|
||||
.gate AND A=$abc$2385$new_n289 B=$abc$2385$new_n292 Y=$abc$2385$new_n366
|
||||
.gate OR A=:1.test_2[0] B=$abc$2385$new_n75 Y=$abc$2385$new_n367
|
||||
.gate AND A=$abc$2385$new_n261 B=$abc$2385$new_n367 Y=$abc$2385$new_n368
|
||||
.gate XNOR A=$abc$2385$new_n270 B=$abc$2385$new_n368 Y=$abc$2385$new_n369
|
||||
.gate XNOR A=$abc$2385$new_n276 B=$abc$2385$new_n369 Y=$abc$2385$new_n370
|
||||
.gate ANDNOT A=:1.test_2[2] B=$abc$2385$new_n77 Y=$abc$2385$new_n371
|
||||
.gate ANDNOT A=:1.test_2[5] B=$abc$2385$new_n91 Y=$abc$2385$new_n372
|
||||
.gate ANDNOT A=:1.test_2[4] B=$abc$2385$new_n103 Y=$abc$2385$new_n373
|
||||
.gate XNOR A=$abc$2385$new_n372 B=$abc$2385$new_n373 Y=$abc$2385$new_n374
|
||||
.gate XNOR A=$abc$2385$new_n371 B=$abc$2385$new_n374 Y=$abc$2385$new_n375
|
||||
.gate XOR A=$abc$2385$new_n260 B=$abc$2385$new_n265 Y=$abc$2385$new_n376
|
||||
.gate XNOR A=$abc$2385$new_n375 B=$abc$2385$new_n376 Y=$abc$2385$new_n377
|
||||
.gate NAND A=$abc$2385$new_n266 B=$abc$2385$new_n268 Y=$abc$2385$new_n378
|
||||
.gate ANDNOT A=:1.test_2[7] B=:1.test_1[0] Y=$abc$2385$new_n379
|
||||
.gate XNOR A=$abc$2385$new_n278 B=$abc$2385$new_n379 Y=$abc$2385$new_n380
|
||||
.gate XNOR A=$abc$2385$new_n75 B=$abc$2385$new_n380 Y=$abc$2385$new_n381
|
||||
.gate XNOR A=$abc$2385$new_n378 B=$abc$2385$new_n381 Y=$abc$2385$new_n382
|
||||
.gate XNOR A=$abc$2385$new_n377 B=$abc$2385$new_n382 Y=$abc$2385$new_n383
|
||||
.gate XNOR A=$abc$2385$new_n370 B=$abc$2385$new_n383 Y=$abc$2385$new_n384
|
||||
.gate NAND A=$abc$2385$new_n283 B=$abc$2385$new_n285 Y=$abc$2385$new_n385
|
||||
.gate AND A=$abc$2385$new_n272 B=$abc$2385$new_n287 Y=$abc$2385$new_n386
|
||||
.gate XNOR A=$abc$2385$new_n385 B=$abc$2385$new_n386 Y=$abc$2385$new_n387
|
||||
.gate XNOR A=$abc$2385$new_n384 B=$abc$2385$new_n387 Y=$abc$2385$new_n388
|
||||
.gate XNOR A=$abc$2385$new_n366 B=$abc$2385$new_n388 Y=$abc$2385$new_n389
|
||||
.gate XNOR A=:1.test_2[7] B=$abc$2385$new_n294 Y=$abc$2385$new_n390
|
||||
.gate XNOR A=$abc$2385$new_n389 B=$abc$2385$new_n390 Y=$abc$2385$new_n391
|
||||
.gate XNOR A=$abc$2385$new_n365 B=$abc$2385$new_n391 Y=$abc$2385$new_n392
|
||||
.gate OR A=in_b_var[6] B=$abc$2385$new_n299 Y=$abc$2385$new_n393
|
||||
.gate ORNOT A=in_b_var[6] B=in_a_var[6] Y=$abc$2385$new_n394
|
||||
.gate ORNOT A=in_a_var[5] B=in_b_var[5] Y=$abc$2385$new_n395
|
||||
.gate ORNOT A=in_b_var[5] B=in_a_var[5] Y=$abc$2385$new_n396
|
||||
.gate ORNOT A=in_b_var[4] B=in_a_var[4] Y=$abc$2385$new_n397
|
||||
.gate AND A=$abc$2385$new_n396 B=$abc$2385$new_n397 Y=$abc$2385$new_n398
|
||||
.gate ORNOT A=in_b_var[2] B=in_a_var[2] Y=$abc$2385$new_n399
|
||||
.gate ORNOT A=in_b_var[3] B=in_a_var[3] Y=$abc$2385$new_n400
|
||||
.gate NAND A=$abc$2385$new_n399 B=$abc$2385$new_n400 Y=$abc$2385$new_n401
|
||||
.gate ORNOT A=in_a_var[3] B=in_b_var[3] Y=$abc$2385$new_n402
|
||||
.gate NAND A=$abc$2385$new_n401 B=$abc$2385$new_n402 Y=$abc$2385$new_n403
|
||||
.gate ORNOT A=in_a_var[2] B=in_b_var[2] Y=$abc$2385$new_n404
|
||||
.gate NAND A=$abc$2385$new_n402 B=$abc$2385$new_n404 Y=$abc$2385$new_n405
|
||||
.gate NOR A=$abc$2385$new_n401 B=$abc$2385$new_n405 Y=$abc$2385$new_n406
|
||||
.gate ORNOT A=in_a_var[0] B=in_b_var[0] Y=$abc$2385$new_n407
|
||||
.gate ORNOT A=in_a_var[1] B=in_b_var[1] Y=$abc$2385$new_n408
|
||||
.gate NAND A=$abc$2385$new_n407 B=$abc$2385$new_n408 Y=$abc$2385$new_n409
|
||||
.gate ORNOT A=in_b_var[1] B=in_a_var[1] Y=$abc$2385$new_n410
|
||||
.gate NAND A=$abc$2385$new_n409 B=$abc$2385$new_n410 Y=$abc$2385$new_n411
|
||||
.gate NAND A=$abc$2385$new_n406 B=$abc$2385$new_n411 Y=$abc$2385$new_n412
|
||||
.gate NAND A=$abc$2385$new_n403 B=$abc$2385$new_n412 Y=$abc$2385$new_n413
|
||||
.gate ORNOT A=in_a_var[4] B=in_b_var[4] Y=$abc$2385$new_n414
|
||||
.gate NAND A=$abc$2385$new_n413 B=$abc$2385$new_n414 Y=$abc$2385$new_n415
|
||||
.gate NAND A=$abc$2385$new_n398 B=$abc$2385$new_n415 Y=$abc$2385$new_n416
|
||||
.gate NAND A=$abc$2385$new_n395 B=$abc$2385$new_n416 Y=$abc$2385$new_n417
|
||||
.gate NAND A=$abc$2385$new_n394 B=$abc$2385$new_n417 Y=$abc$2385$new_n418
|
||||
.gate NAND A=$abc$2385$new_n394 B=$abc$2385$new_n395 Y=$abc$2385$new_n419
|
||||
.gate NOR A=$abc$2385$new_n409 B=$abc$2385$new_n419 Y=$abc$2385$new_n420
|
||||
.gate AND A=$abc$2385$new_n398 B=$abc$2385$new_n420 Y=$abc$2385$new_n421
|
||||
.gate ORNOT A=in_b_var[0] B=in_a_var[0] Y=$abc$2385$new_n422
|
||||
.gate AND A=$abc$2385$new_n410 B=$abc$2385$new_n414 Y=$abc$2385$new_n423
|
||||
.gate AND A=$abc$2385$new_n422 B=$abc$2385$new_n423 Y=$abc$2385$new_n424
|
||||
.gate AND A=$abc$2385$new_n406 B=$abc$2385$new_n424 Y=$abc$2385$new_n425
|
||||
.gate NAND A=$abc$2385$new_n421 B=$abc$2385$new_n425 Y=$abc$2385$new_n426
|
||||
.gate ORNOT A=in_a_var[6] B=in_b_var[6] Y=$abc$2385$new_n427
|
||||
.gate AND A=$abc$2385$new_n151 B=$abc$2385$new_n427 Y=$abc$2385$new_n428
|
||||
.gate AND A=$abc$2385$new_n426 B=$abc$2385$new_n428 Y=$abc$2385$new_n429
|
||||
.gate AND A=$abc$2385$new_n418 B=$abc$2385$new_n429 Y=$abc$2385$new_n430
|
||||
.gate AND A=$abc$2385$new_n393 B=$abc$2385$new_n430 Y=$abc$2385$new_n431
|
||||
.gate AND A=$abc$2385$new_n392 B=$abc$2385$new_n431 Y=$abc$2385$new_n432
|
||||
.gate AND A=$abc$2385$new_n364 B=$abc$2385$new_n432 Y=$abc$2385$new_n433
|
||||
.gate AND A=$abc$2385$new_n358 B=$abc$2385$new_n433 Y=$abc$2385$new_n434
|
||||
.gate AND A=$abc$2385$new_n332 B=$abc$2385$new_n434 Y=$abc$2385$new_n435
|
||||
.gate AND A=$abc$2385$new_n157 B=$abc$2385$new_n435 Y=$abc$2385$new_n436
|
||||
.gate XNOR A=$abc$2385$new_n157 B=$abc$2385$new_n435 Y=$abc$2385$new_n437
|
||||
.gate ORNOT A=$abc$2385$new_n74 B=:1.test_1[0] Y=$abc$2385$new_n438
|
||||
.gate MUX A=:1.test_1[0] B=$abc$2385$new_n437 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[0]
|
||||
.gate ORNOT A=:1.test_1[1] B=$abc$2385$new_n83 Y=$abc$2385$new_n440
|
||||
.gate XNOR A=$abc$2385$new_n320 B=$abc$2385$new_n436 Y=$abc$2385$new_n441
|
||||
.gate MUX A=$abc$2385$new_n440 B=$abc$2385$new_n441 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[1]
|
||||
.gate ORNOT A=:1.test_1[2] B=$abc$2385$new_n83 Y=$abc$2385$new_n443
|
||||
.gate ANDNOT A=$abc$2385$new_n308 B=$abc$2385$new_n359 Y=$abc$2385$new_n444
|
||||
.gate XNOR A=$abc$2385$new_n308 B=$abc$2385$new_n359 Y=$abc$2385$new_n445
|
||||
.gate NAND A=$abc$2385$new_n435 B=$abc$2385$new_n445 Y=$abc$2385$new_n446
|
||||
.gate ORNOT A=$abc$2385$new_n435 B=$abc$2385$new_n308 Y=$abc$2385$new_n447
|
||||
.gate AND A=$abc$2385$new_n74 B=$abc$2385$new_n446 Y=$abc$2385$new_n448
|
||||
.gate NAND A=$abc$2385$new_n447 B=$abc$2385$new_n448 Y=$abc$2385$new_n449
|
||||
.gate AND A=$abc$2385$new_n443 B=$abc$2385$new_n449 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[2]
|
||||
.gate ORNOT A=:1.test_1[3] B=$abc$2385$new_n83 Y=$abc$2385$new_n451
|
||||
.gate AND A=$abc$2385$new_n435 B=$abc$2385$new_n444 Y=$abc$2385$new_n452
|
||||
.gate AND A=$abc$2385$new_n304 B=$abc$2385$new_n452 Y=$abc$2385$new_n453
|
||||
.gate XNOR A=$abc$2385$new_n305 B=$abc$2385$new_n452 Y=$abc$2385$new_n454
|
||||
.gate MUX A=$abc$2385$new_n451 B=$abc$2385$new_n454 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[3]
|
||||
.gate ORNOT A=:1.test_1[4] B=$abc$2385$new_n83 Y=$abc$2385$new_n456
|
||||
.gate ORNOT A=$abc$2385$new_n303 B=$abc$2385$new_n453 Y=$abc$2385$new_n457
|
||||
.gate XNOR A=$abc$2385$new_n303 B=$abc$2385$new_n453 Y=$abc$2385$new_n458
|
||||
.gate MUX A=$abc$2385$new_n456 B=$abc$2385$new_n458 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[4]
|
||||
.gate ORNOT A=:1.test_1[5] B=$abc$2385$new_n83 Y=$abc$2385$new_n460
|
||||
.gate OR A=$abc$2385$new_n302 B=$abc$2385$new_n457 Y=$abc$2385$new_n461
|
||||
.gate XOR A=$abc$2385$new_n302 B=$abc$2385$new_n457 Y=$abc$2385$new_n462
|
||||
.gate NAND A=$abc$2385$new_n74 B=$abc$2385$new_n462 Y=$abc$2385$new_n463
|
||||
.gate NAND A=$abc$2385$new_n460 B=$abc$2385$new_n463 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[5]
|
||||
.gate NAND A=$abc$2385$new_n299 B=$abc$2385$new_n461 Y=$abc$2385$new_n465
|
||||
.gate OR A=$abc$2385$new_n299 B=$abc$2385$new_n461 Y=$abc$2385$new_n466
|
||||
.gate AND A=$abc$2385$new_n74 B=$abc$2385$new_n466 Y=$abc$2385$new_n467
|
||||
.gate NAND A=$abc$2385$new_n465 B=$abc$2385$new_n467 Y=$abc$2385$new_n468
|
||||
.gate MUX A=$abc$2385$new_n73 B=$abc$2385$new_n137 S=$abc$2385$new_n76 Y=$abc$2385$new_n469
|
||||
.gate OR A=$abc$2385$new_n74 B=$abc$2385$new_n469 Y=$abc$2385$new_n470
|
||||
.gate NAND A=$abc$2385$new_n468 B=$abc$2385$new_n470 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[6]
|
||||
.gate NAND A=$abc$2385$new_n392 B=$abc$2385$new_n467 Y=$abc$2385$new_n472
|
||||
.gate ANDNOT A=$abc$2385$new_n137 B=$abc$2385$new_n76 Y=$abc$2385$new_n473
|
||||
.gate XNOR A=$abc$2385$new_n150 B=$abc$2385$new_n473 Y=$abc$2385$new_n474
|
||||
.gate AND A=$abc$2385$new_n472 B=$abc$2385$new_n474 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[7]
|
||||
.gate AND A=$abc$2385$new_n58 B=$abc$2385$new_n438 Y=:38.Y[0]
|
||||
.gate NAND A=in_a_var[1] B=$abc$2385$new_n74 Y=$abc$2385$new_n477
|
||||
.gate NAND A=$abc$2385$new_n84 B=$abc$2385$new_n477 Y=:38.Y[1]
|
||||
.gate NAND A=in_a_var[2] B=$abc$2385$new_n74 Y=$abc$2385$new_n479
|
||||
.gate NAND A=$abc$2385$new_n92 B=$abc$2385$new_n479 Y=:38.Y[2]
|
||||
.gate NAND A=in_a_var[3] B=$abc$2385$new_n74 Y=$abc$2385$new_n481
|
||||
.gate NAND A=$abc$2385$new_n104 B=$abc$2385$new_n481 Y=:38.Y[3]
|
||||
.gate NAND A=in_a_var[4] B=$abc$2385$new_n74 Y=$abc$2385$new_n483
|
||||
.gate NAND A=$abc$2385$new_n116 B=$abc$2385$new_n483 Y=:38.Y[4]
|
||||
.gate NAND A=in_a_var[5] B=$abc$2385$new_n74 Y=$abc$2385$new_n485
|
||||
.gate NAND A=$abc$2385$new_n127 B=$abc$2385$new_n485 Y=:38.Y[5]
|
||||
.gate NAND A=in_a_var[6] B=$abc$2385$new_n74 Y=$abc$2385$new_n487
|
||||
.gate NAND A=$abc$2385$new_n137 B=$abc$2385$new_n487 Y=:38.Y[6]
|
||||
.gate NAND A=in_a_var[7] B=$abc$2385$new_n74 Y=$abc$2385$new_n489
|
||||
.gate NAND A=$abc$2385$new_n150 B=$abc$2385$new_n489 Y=:38.Y[7]
|
||||
.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:114:fulladd$252.Y[0] Q=out_var[0]
|
||||
.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.P[1] Q=out_var[1]
|
||||
.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[2] Q=out_var[2]
|
||||
.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[3] Q=out_var[3]
|
||||
.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[4] Q=out_var[4]
|
||||
.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[5] Q=out_var[5]
|
||||
.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[6] Q=out_var[6]
|
||||
.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[7] Q=out_var[7]
|
||||
.gate DFF C=clk D=:38.Y[0] Q=:1.test_1[0]
|
||||
.gate DFF C=clk D=:38.Y[1] Q=:1.test_1[1]
|
||||
.gate DFF C=clk D=:38.Y[2] Q=:1.test_1[2]
|
||||
.gate DFF C=clk D=:38.Y[3] Q=:1.test_1[3]
|
||||
.gate DFF C=clk D=:38.Y[4] Q=:1.test_1[4]
|
||||
.gate DFF C=clk D=:38.Y[5] Q=:1.test_1[5]
|
||||
.gate DFF C=clk D=:38.Y[6] Q=:1.test_1[6]
|
||||
.gate DFF C=clk D=:38.Y[7] Q=:1.test_1[7]
|
||||
.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[0] Q=:1.test_2[0]
|
||||
.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[1] Q=:1.test_2[1]
|
||||
.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[2] Q=:1.test_2[2]
|
||||
.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[3] Q=:1.test_2[3]
|
||||
.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[4] Q=:1.test_2[4]
|
||||
.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[5] Q=:1.test_2[5]
|
||||
.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[6] Q=:1.test_2[6]
|
||||
.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[7] Q=:1.test_2[7]
|
||||
.gateinit :1.test_2[7]=0
|
||||
.gateinit :1.test_2[6]=0
|
||||
.gateinit :1.test_2[5]=0
|
||||
.gateinit :1.test_2[4]=0
|
||||
.gateinit :1.test_2[3]=0
|
||||
.gateinit :1.test_2[2]=0
|
||||
.gateinit :1.test_2[1]=0
|
||||
.gateinit :1.test_2[0]=0
|
||||
.gateinit :1.test_1[7]=1
|
||||
.gateinit :1.test_1[6]=1
|
||||
.gateinit :1.test_1[5]=1
|
||||
.gateinit :1.test_1[4]=1
|
||||
.gateinit :1.test_1[3]=1
|
||||
.gateinit :1.test_1[2]=1
|
||||
.gateinit :1.test_1[1]=1
|
||||
.gateinit :1.test_1[0]=1
|
||||
.end
|
||||
484
tests/blif/gatesi.blif.ok
Normal file
484
tests/blif/gatesi.blif.ok
Normal file
|
|
@ -0,0 +1,484 @@
|
|||
# Generated by Yosys
|
||||
|
||||
.model test
|
||||
.inputs clk in_a_var[0] in_a_var[1] in_a_var[2] in_a_var[3] in_a_var[4] in_a_var[5] in_a_var[6] in_a_var[7] in_b_var[0] in_b_var[1] in_b_var[2] in_b_var[3] in_b_var[4] in_b_var[5] in_b_var[6] in_b_var[7]
|
||||
.outputs out_var[0] out_var[1] out_var[2] out_var[3] out_var[4] out_var[5] out_var[6] out_var[7]
|
||||
.names $false
|
||||
.names $true
|
||||
1
|
||||
.names $undef
|
||||
.subckt ORNOT A=:1.test_1[0] B=in_a_var[0] Y=$abc$2385$new_n57
|
||||
.subckt NOT A=$abc$2385$new_n65 Y=$abc$2385$new_n66
|
||||
.subckt XNOR A=$abc$2385$new_n62 B=$abc$2385$new_n88 Y=$abc$2385$auto$maccmap.cc:240:synth$253.P[1]
|
||||
.subckt NAND A=:1.test_1[0] B=:1.test_2[0] Y=$abc$2385$new_n157
|
||||
.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n91 Y=$abc$2385$new_n158
|
||||
.subckt ANDNOT A=:1.test_2[1] B=$abc$2385$new_n64 Y=$abc$2385$new_n159
|
||||
.subckt AND A=:1.test_2[1] B=$abc$2385$new_n65 Y=$abc$2385$new_n160
|
||||
.subckt ORNOT A=$abc$2385$new_n160 B=:1.test_1[0] Y=$abc$2385$new_n161
|
||||
.subckt AND A=:1.test_2[2] B=$abc$2385$new_n161 Y=$abc$2385$new_n162
|
||||
.subckt ANDNOT A=:1.test_1[1] B=:1.test_1[0] Y=$abc$2385$new_n163
|
||||
.subckt ANDNOT A=:1.test_2[2] B=:1.test_1[0] Y=$abc$2385$new_n164
|
||||
.subckt XNOR A=$abc$2385$new_n160 B=$abc$2385$new_n164 Y=$abc$2385$new_n165
|
||||
.subckt AND A=:1.test_1[2] B=$abc$2385$new_n64 Y=$abc$2385$new_n67
|
||||
.subckt MUX A=$abc$2385$new_n160 B=$abc$2385$new_n165 S=:1.test_2[2] Y=$abc$2385$new_n166
|
||||
.subckt ORNOT A=:1.test_2[0] B=:1.test_1[0] Y=$abc$2385$new_n167
|
||||
.subckt AND A=$abc$2385$new_n159 B=$abc$2385$new_n167 Y=$abc$2385$new_n168
|
||||
.subckt AND A=$abc$2385$new_n166 B=$abc$2385$new_n168 Y=$abc$2385$new_n169
|
||||
.subckt XOR A=$abc$2385$new_n166 B=$abc$2385$new_n168 Y=$abc$2385$new_n170
|
||||
.subckt AND A=$abc$2385$new_n158 B=$abc$2385$new_n170 Y=$abc$2385$new_n171
|
||||
.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n103 Y=$abc$2385$new_n172
|
||||
.subckt ANDNOT A=:1.test_2[1] B=$abc$2385$new_n91 Y=$abc$2385$new_n173
|
||||
.subckt ANDNOT A=:1.test_2[1] B=$abc$2385$new_n103 Y=$abc$2385$new_n174
|
||||
.subckt AND A=$abc$2385$new_n158 B=$abc$2385$new_n174 Y=$abc$2385$new_n175
|
||||
.subckt AND A=:1.test_1[3] B=$abc$2385$new_n67 Y=$abc$2385$new_n68
|
||||
.subckt XOR A=$abc$2385$new_n172 B=$abc$2385$new_n173 Y=$abc$2385$new_n176
|
||||
.subckt NAND A=:1.test_2[2] B=$abc$2385$new_n65 Y=$abc$2385$new_n177
|
||||
.subckt AND A=:1.test_1[0] B=:1.test_2[3] Y=$abc$2385$new_n178
|
||||
.subckt NAND A=:1.test_1[0] B=$abc$2385$new_n177 Y=$abc$2385$new_n179
|
||||
.subckt XNOR A=$abc$2385$new_n177 B=$abc$2385$new_n178 Y=$abc$2385$new_n180
|
||||
.subckt NAND A=$abc$2385$new_n162 B=$abc$2385$new_n180 Y=$abc$2385$new_n181
|
||||
.subckt XOR A=$abc$2385$new_n162 B=$abc$2385$new_n180 Y=$abc$2385$new_n182
|
||||
.subckt NAND A=$abc$2385$new_n176 B=$abc$2385$new_n182 Y=$abc$2385$new_n183
|
||||
.subckt XOR A=$abc$2385$new_n176 B=$abc$2385$new_n182 Y=$abc$2385$new_n184
|
||||
.subckt NAND A=$abc$2385$new_n171 B=$abc$2385$new_n184 Y=$abc$2385$new_n185
|
||||
.subckt AND A=:1.test_1[4] B=$abc$2385$new_n68 Y=$abc$2385$new_n69
|
||||
.subckt XOR A=$abc$2385$new_n171 B=$abc$2385$new_n184 Y=$abc$2385$new_n186
|
||||
.subckt NAND A=$abc$2385$new_n169 B=$abc$2385$new_n186 Y=$abc$2385$new_n187
|
||||
.subckt NAND A=$abc$2385$new_n185 B=$abc$2385$new_n187 Y=$abc$2385$new_n188
|
||||
.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n115 Y=$abc$2385$new_n189
|
||||
.subckt ANDNOT A=:1.test_2[1] B=$abc$2385$new_n115 Y=$abc$2385$new_n190
|
||||
.subckt NAND A=$abc$2385$new_n172 B=$abc$2385$new_n190 Y=$abc$2385$new_n191
|
||||
.subckt XOR A=$abc$2385$new_n174 B=$abc$2385$new_n189 Y=$abc$2385$new_n192
|
||||
.subckt ANDNOT A=:1.test_2[2] B=$abc$2385$new_n91 Y=$abc$2385$new_n193
|
||||
.subckt NAND A=$abc$2385$new_n192 B=$abc$2385$new_n193 Y=$abc$2385$new_n194
|
||||
.subckt XOR A=$abc$2385$new_n192 B=$abc$2385$new_n193 Y=$abc$2385$new_n195
|
||||
.subckt AND A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n70
|
||||
.subckt AND A=:1.test_2[3] B=$abc$2385$new_n179 Y=$abc$2385$new_n196
|
||||
.subckt NAND A=:1.test_2[3] B=$abc$2385$new_n65 Y=$abc$2385$new_n197
|
||||
.subckt NAND A=:1.test_1[0] B=$abc$2385$new_n197 Y=$abc$2385$new_n198
|
||||
.subckt AND A=:1.test_2[4] B=$abc$2385$new_n198 Y=$abc$2385$new_n199
|
||||
.subckt NAND A=:1.test_2[3] B=$abc$2385$new_n163 Y=$abc$2385$new_n200
|
||||
.subckt NAND A=$abc$2385$new_n199 B=$abc$2385$new_n200 Y=$abc$2385$new_n201
|
||||
.subckt ORNOT A=:1.test_2[4] B=$abc$2385$new_n197 Y=$abc$2385$new_n202
|
||||
.subckt AND A=$abc$2385$new_n201 B=$abc$2385$new_n202 Y=$abc$2385$new_n203
|
||||
.subckt NAND A=$abc$2385$new_n175 B=$abc$2385$new_n203 Y=$abc$2385$new_n204
|
||||
.subckt XOR A=$abc$2385$new_n175 B=$abc$2385$new_n203 Y=$abc$2385$new_n205
|
||||
.subckt AND A=:1.test_1[6] B=$abc$2385$new_n70 Y=$abc$2385$new_n71
|
||||
.subckt NAND A=$abc$2385$new_n196 B=$abc$2385$new_n205 Y=$abc$2385$new_n206
|
||||
.subckt XOR A=$abc$2385$new_n196 B=$abc$2385$new_n205 Y=$abc$2385$new_n207
|
||||
.subckt AND A=$abc$2385$new_n195 B=$abc$2385$new_n207 Y=$abc$2385$new_n208
|
||||
.subckt XOR A=$abc$2385$new_n195 B=$abc$2385$new_n207 Y=$abc$2385$new_n209
|
||||
.subckt NAND A=$abc$2385$new_n181 B=$abc$2385$new_n183 Y=$abc$2385$new_n210
|
||||
.subckt AND A=$abc$2385$new_n209 B=$abc$2385$new_n210 Y=$abc$2385$new_n211
|
||||
.subckt XOR A=$abc$2385$new_n209 B=$abc$2385$new_n210 Y=$abc$2385$new_n212
|
||||
.subckt AND A=$abc$2385$new_n188 B=$abc$2385$new_n212 Y=$abc$2385$new_n213
|
||||
.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n77 Y=$abc$2385$new_n214
|
||||
.subckt ANDNOT A=:1.test_2[3] B=$abc$2385$new_n91 Y=$abc$2385$new_n215
|
||||
.subckt XNOR A=:1.test_1[6] B=$abc$2385$new_n70 Y=$abc$2385$new_n72
|
||||
.subckt ANDNOT A=:1.test_2[2] B=$abc$2385$new_n103 Y=$abc$2385$new_n216
|
||||
.subckt ANDNOT A=:1.test_2[2] B=$abc$2385$new_n115 Y=$abc$2385$new_n217
|
||||
.subckt NAND A=$abc$2385$new_n174 B=$abc$2385$new_n217 Y=$abc$2385$new_n218
|
||||
.subckt XOR A=$abc$2385$new_n190 B=$abc$2385$new_n216 Y=$abc$2385$new_n219
|
||||
.subckt NAND A=$abc$2385$new_n215 B=$abc$2385$new_n219 Y=$abc$2385$new_n220
|
||||
.subckt XOR A=$abc$2385$new_n215 B=$abc$2385$new_n219 Y=$abc$2385$new_n221
|
||||
.subckt AND A=$abc$2385$new_n214 B=$abc$2385$new_n221 Y=$abc$2385$new_n222
|
||||
.subckt XOR A=$abc$2385$new_n214 B=$abc$2385$new_n221 Y=$abc$2385$new_n223
|
||||
.subckt NAND A=:1.test_2[4] B=$abc$2385$new_n65 Y=$abc$2385$new_n224
|
||||
.subckt NAND A=:1.test_1[0] B=$abc$2385$new_n224 Y=$abc$2385$new_n225
|
||||
.subckt NOT A=$abc$2385$new_n72 Y=$abc$2385$new_n73
|
||||
.subckt AND A=:1.test_2[5] B=$abc$2385$new_n225 Y=$abc$2385$new_n226
|
||||
.subckt NAND A=:1.test_2[4] B=$abc$2385$new_n163 Y=$abc$2385$new_n227
|
||||
.subckt NAND A=$abc$2385$new_n226 B=$abc$2385$new_n227 Y=$abc$2385$new_n228
|
||||
.subckt ORNOT A=:1.test_2[5] B=$abc$2385$new_n224 Y=$abc$2385$new_n229
|
||||
.subckt AND A=$abc$2385$new_n228 B=$abc$2385$new_n229 Y=$abc$2385$new_n230
|
||||
.subckt NAND A=$abc$2385$new_n191 B=$abc$2385$new_n194 Y=$abc$2385$new_n231
|
||||
.subckt NAND A=$abc$2385$new_n230 B=$abc$2385$new_n231 Y=$abc$2385$new_n232
|
||||
.subckt XOR A=$abc$2385$new_n230 B=$abc$2385$new_n231 Y=$abc$2385$new_n233
|
||||
.subckt NAND A=$abc$2385$new_n199 B=$abc$2385$new_n233 Y=$abc$2385$new_n234
|
||||
.subckt XOR A=$abc$2385$new_n199 B=$abc$2385$new_n233 Y=$abc$2385$new_n235
|
||||
.subckt AND A=:1.test_1[7] B=$abc$2385$new_n71 Y=$abc$2385$new_n74
|
||||
.subckt AND A=$abc$2385$new_n223 B=$abc$2385$new_n235 Y=$abc$2385$new_n236
|
||||
.subckt XOR A=$abc$2385$new_n223 B=$abc$2385$new_n235 Y=$abc$2385$new_n237
|
||||
.subckt NAND A=$abc$2385$new_n208 B=$abc$2385$new_n237 Y=$abc$2385$new_n238
|
||||
.subckt XOR A=$abc$2385$new_n208 B=$abc$2385$new_n237 Y=$abc$2385$new_n239
|
||||
.subckt NAND A=$abc$2385$new_n204 B=$abc$2385$new_n206 Y=$abc$2385$new_n240
|
||||
.subckt NAND A=$abc$2385$new_n239 B=$abc$2385$new_n240 Y=$abc$2385$new_n241
|
||||
.subckt XOR A=$abc$2385$new_n239 B=$abc$2385$new_n240 Y=$abc$2385$new_n242
|
||||
.subckt AND A=$abc$2385$new_n211 B=$abc$2385$new_n242 Y=$abc$2385$new_n243
|
||||
.subckt XOR A=$abc$2385$new_n211 B=$abc$2385$new_n242 Y=$abc$2385$new_n244
|
||||
.subckt NAND A=$abc$2385$new_n213 B=$abc$2385$new_n244 Y=$abc$2385$new_n245
|
||||
.subckt XNOR A=:1.test_1[7] B=$abc$2385$new_n71 Y=$abc$2385$new_n75
|
||||
.subckt AND A=:1.test_2[0] B=$abc$2385$new_n163 Y=$abc$2385$new_n246
|
||||
.subckt NAND A=:1.test_2[0] B=$abc$2385$new_n163 Y=$abc$2385$new_n247
|
||||
.subckt XOR A=$abc$2385$new_n158 B=$abc$2385$new_n170 Y=$abc$2385$new_n248
|
||||
.subckt AND A=$abc$2385$new_n246 B=$abc$2385$new_n248 Y=$abc$2385$new_n249
|
||||
.subckt XOR A=$abc$2385$new_n169 B=$abc$2385$new_n186 Y=$abc$2385$new_n250
|
||||
.subckt AND A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n251
|
||||
.subckt XOR A=$abc$2385$new_n188 B=$abc$2385$new_n212 Y=$abc$2385$new_n252
|
||||
.subckt AND A=$abc$2385$new_n251 B=$abc$2385$new_n252 Y=$abc$2385$new_n253
|
||||
.subckt NAND A=$abc$2385$new_n244 B=$abc$2385$new_n253 Y=$abc$2385$new_n254
|
||||
.subckt XNOR A=$abc$2385$new_n213 B=$abc$2385$new_n244 Y=$abc$2385$new_n255
|
||||
.subckt ORNOT A=in_a_var[0] B=:1.test_1[0] Y=$abc$2385$new_n58
|
||||
.subckt ANDNOT A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n76
|
||||
.subckt NAND A=$abc$2385$new_n245 B=$abc$2385$new_n254 Y=$abc$2385$new_n256
|
||||
.subckt NAND A=$abc$2385$new_n238 B=$abc$2385$new_n241 Y=$abc$2385$new_n257
|
||||
.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n72 Y=$abc$2385$new_n258
|
||||
.subckt ORNOT A=$abc$2385$new_n77 B=:1.test_2[1] Y=$abc$2385$new_n259
|
||||
.subckt ANDNOT A=:1.test_2[1] B=$abc$2385$new_n72 Y=$abc$2385$new_n260
|
||||
.subckt NAND A=$abc$2385$new_n214 B=$abc$2385$new_n260 Y=$abc$2385$new_n261
|
||||
.subckt XNOR A=$abc$2385$new_n258 B=$abc$2385$new_n259 Y=$abc$2385$new_n262
|
||||
.subckt ANDNOT A=:1.test_2[4] B=$abc$2385$new_n91 Y=$abc$2385$new_n263
|
||||
.subckt ANDNOT A=:1.test_2[3] B=$abc$2385$new_n103 Y=$abc$2385$new_n264
|
||||
.subckt ANDNOT A=:1.test_2[3] B=$abc$2385$new_n115 Y=$abc$2385$new_n265
|
||||
.subckt XNOR A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n77
|
||||
.subckt NAND A=$abc$2385$new_n216 B=$abc$2385$new_n265 Y=$abc$2385$new_n266
|
||||
.subckt XOR A=$abc$2385$new_n217 B=$abc$2385$new_n264 Y=$abc$2385$new_n267
|
||||
.subckt NAND A=$abc$2385$new_n263 B=$abc$2385$new_n267 Y=$abc$2385$new_n268
|
||||
.subckt XOR A=$abc$2385$new_n263 B=$abc$2385$new_n267 Y=$abc$2385$new_n269
|
||||
.subckt AND A=$abc$2385$new_n262 B=$abc$2385$new_n269 Y=$abc$2385$new_n270
|
||||
.subckt XOR A=$abc$2385$new_n262 B=$abc$2385$new_n269 Y=$abc$2385$new_n271
|
||||
.subckt NAND A=$abc$2385$new_n222 B=$abc$2385$new_n271 Y=$abc$2385$new_n272
|
||||
.subckt XOR A=$abc$2385$new_n222 B=$abc$2385$new_n271 Y=$abc$2385$new_n273
|
||||
.subckt NAND A=:1.test_2[5] B=$abc$2385$new_n65 Y=$abc$2385$new_n274
|
||||
.subckt NAND A=:1.test_1[0] B=$abc$2385$new_n274 Y=$abc$2385$new_n275
|
||||
.subckt NOR A=:1.test_1[3] B=:1.test_1[4] Y=$abc$2385$new_n78
|
||||
.subckt AND A=:1.test_2[6] B=$abc$2385$new_n275 Y=$abc$2385$new_n276
|
||||
.subckt NAND A=:1.test_2[5] B=$abc$2385$new_n163 Y=$abc$2385$new_n277
|
||||
.subckt NAND A=:1.test_2[6] B=$abc$2385$new_n65 Y=$abc$2385$new_n278
|
||||
.subckt NAND A=$abc$2385$new_n276 B=$abc$2385$new_n277 Y=$abc$2385$new_n279
|
||||
.subckt ORNOT A=:1.test_2[6] B=$abc$2385$new_n274 Y=$abc$2385$new_n280
|
||||
.subckt AND A=$abc$2385$new_n279 B=$abc$2385$new_n280 Y=$abc$2385$new_n281
|
||||
.subckt NAND A=$abc$2385$new_n218 B=$abc$2385$new_n220 Y=$abc$2385$new_n282
|
||||
.subckt NAND A=$abc$2385$new_n281 B=$abc$2385$new_n282 Y=$abc$2385$new_n283
|
||||
.subckt XOR A=$abc$2385$new_n281 B=$abc$2385$new_n282 Y=$abc$2385$new_n284
|
||||
.subckt NAND A=$abc$2385$new_n226 B=$abc$2385$new_n284 Y=$abc$2385$new_n285
|
||||
.subckt AND A=$abc$2385$new_n63 B=$abc$2385$new_n78 Y=$abc$2385$new_n79
|
||||
.subckt XOR A=$abc$2385$new_n226 B=$abc$2385$new_n284 Y=$abc$2385$new_n286
|
||||
.subckt NAND A=$abc$2385$new_n273 B=$abc$2385$new_n286 Y=$abc$2385$new_n287
|
||||
.subckt XOR A=$abc$2385$new_n273 B=$abc$2385$new_n286 Y=$abc$2385$new_n288
|
||||
.subckt NAND A=$abc$2385$new_n236 B=$abc$2385$new_n288 Y=$abc$2385$new_n289
|
||||
.subckt XOR A=$abc$2385$new_n236 B=$abc$2385$new_n288 Y=$abc$2385$new_n290
|
||||
.subckt NAND A=$abc$2385$new_n232 B=$abc$2385$new_n234 Y=$abc$2385$new_n291
|
||||
.subckt NAND A=$abc$2385$new_n290 B=$abc$2385$new_n291 Y=$abc$2385$new_n292
|
||||
.subckt XOR A=$abc$2385$new_n290 B=$abc$2385$new_n291 Y=$abc$2385$new_n293
|
||||
.subckt NAND A=$abc$2385$new_n257 B=$abc$2385$new_n293 Y=$abc$2385$new_n294
|
||||
.subckt XOR A=$abc$2385$new_n257 B=$abc$2385$new_n293 Y=$abc$2385$new_n295
|
||||
.subckt ANDNOT A=$abc$2385$new_n79 B=:1.test_1[2] Y=$abc$2385$new_n80
|
||||
.subckt NAND A=$abc$2385$new_n243 B=$abc$2385$new_n295 Y=$abc$2385$new_n296
|
||||
.subckt XOR A=$abc$2385$new_n243 B=$abc$2385$new_n295 Y=$abc$2385$new_n297
|
||||
.subckt NAND A=$abc$2385$new_n256 B=$abc$2385$new_n297 Y=$abc$2385$new_n298
|
||||
.subckt XNOR A=$abc$2385$new_n256 B=$abc$2385$new_n297 Y=$abc$2385$new_n299
|
||||
.subckt NAND A=$abc$2385$new_n73 B=$abc$2385$new_n299 Y=$abc$2385$new_n300
|
||||
.subckt OR A=$abc$2385$new_n73 B=$abc$2385$new_n299 Y=$abc$2385$new_n301
|
||||
.subckt XOR A=$abc$2385$new_n253 B=$abc$2385$new_n255 Y=$abc$2385$new_n302
|
||||
.subckt XNOR A=$abc$2385$new_n251 B=$abc$2385$new_n252 Y=$abc$2385$new_n303
|
||||
.subckt XOR A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n304
|
||||
.subckt XNOR A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n305
|
||||
.subckt AND A=$abc$2385$new_n77 B=$abc$2385$new_n80 Y=$abc$2385$new_n81
|
||||
.subckt NAND A=$abc$2385$new_n103 B=$abc$2385$new_n304 Y=$abc$2385$new_n306
|
||||
.subckt OR A=$abc$2385$new_n103 B=$abc$2385$new_n304 Y=$abc$2385$new_n307
|
||||
.subckt XNOR A=$abc$2385$new_n247 B=$abc$2385$new_n248 Y=$abc$2385$new_n308
|
||||
.subckt NAND A=:1.test_1[0] B=:1.test_2[1] Y=$abc$2385$new_n309
|
||||
.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n64 Y=$abc$2385$new_n310
|
||||
.subckt XNOR A=$abc$2385$new_n309 B=$abc$2385$new_n310 Y=$abc$2385$new_n311
|
||||
.subckt NAND A=$abc$2385$new_n66 B=$abc$2385$new_n311 Y=$abc$2385$new_n312
|
||||
.subckt OR A=:1.test_2[1] B=$abc$2385$new_n157 Y=$abc$2385$new_n313
|
||||
.subckt NAND A=$abc$2385$new_n312 B=$abc$2385$new_n313 Y=$abc$2385$new_n314
|
||||
.subckt OR A=$abc$2385$new_n308 B=$abc$2385$new_n314 Y=$abc$2385$new_n315
|
||||
.subckt NAND A=$abc$2385$new_n75 B=$abc$2385$new_n81 Y=$abc$2385$new_n82
|
||||
.subckt NAND A=$abc$2385$new_n91 B=$abc$2385$new_n315 Y=$abc$2385$new_n316
|
||||
.subckt NAND A=$abc$2385$new_n308 B=$abc$2385$new_n314 Y=$abc$2385$new_n317
|
||||
.subckt NAND A=$abc$2385$new_n316 B=$abc$2385$new_n317 Y=$abc$2385$new_n318
|
||||
.subckt NAND A=$abc$2385$new_n307 B=$abc$2385$new_n318 Y=$abc$2385$new_n319
|
||||
.subckt NAND A=$abc$2385$new_n247 B=$abc$2385$new_n311 Y=$abc$2385$new_n320
|
||||
.subckt NAND A=$abc$2385$new_n306 B=$abc$2385$new_n319 Y=$abc$2385$new_n321
|
||||
.subckt ORNOT A=$abc$2385$new_n115 B=$abc$2385$new_n303 Y=$abc$2385$new_n322
|
||||
.subckt ORNOT A=$abc$2385$new_n303 B=$abc$2385$new_n115 Y=$abc$2385$new_n323
|
||||
.subckt NAND A=$abc$2385$new_n321 B=$abc$2385$new_n322 Y=$abc$2385$new_n324
|
||||
.subckt NAND A=$abc$2385$new_n323 B=$abc$2385$new_n324 Y=$abc$2385$new_n325
|
||||
.subckt OR A=$abc$2385$new_n73 B=$abc$2385$new_n82 Y=$abc$2385$new_n83
|
||||
.subckt NAND A=$abc$2385$new_n77 B=$abc$2385$new_n325 Y=$abc$2385$new_n326
|
||||
.subckt NAND A=$abc$2385$new_n302 B=$abc$2385$new_n326 Y=$abc$2385$new_n327
|
||||
.subckt OR A=$abc$2385$new_n77 B=$abc$2385$new_n325 Y=$abc$2385$new_n328
|
||||
.subckt AND A=$abc$2385$new_n327 B=$abc$2385$new_n328 Y=$abc$2385$new_n329
|
||||
.subckt NAND A=$abc$2385$new_n300 B=$abc$2385$new_n329 Y=$abc$2385$new_n330
|
||||
.subckt AND A=$abc$2385$new_n301 B=$abc$2385$new_n330 Y=$abc$2385$new_n331
|
||||
.subckt NAND A=$abc$2385$new_n75 B=$abc$2385$new_n331 Y=$abc$2385$new_n332
|
||||
.subckt OR A=in_b_var[5] B=$abc$2385$new_n302 Y=$abc$2385$new_n333
|
||||
.subckt NAND A=in_b_var[4] B=$abc$2385$new_n303 Y=$abc$2385$new_n334
|
||||
.subckt OR A=in_b_var[4] B=$abc$2385$new_n303 Y=$abc$2385$new_n335
|
||||
.subckt AND A=$abc$2385$new_n66 B=$abc$2385$new_n83 Y=$abc$2385$new_n84
|
||||
.subckt AND A=in_b_var[1] B=$abc$2385$new_n320 Y=$abc$2385$new_n336
|
||||
.subckt OR A=in_b_var[3] B=$abc$2385$new_n305 Y=$abc$2385$new_n337
|
||||
.subckt ANDNOT A=in_b_var[2] B=$abc$2385$new_n308 Y=$abc$2385$new_n338
|
||||
.subckt XNOR A=in_b_var[2] B=$abc$2385$new_n308 Y=$abc$2385$new_n339
|
||||
.subckt NAND A=in_b_var[3] B=$abc$2385$new_n305 Y=$abc$2385$new_n340
|
||||
.subckt XNOR A=in_b_var[3] B=$abc$2385$new_n304 Y=$abc$2385$new_n341
|
||||
.subckt AND A=$abc$2385$new_n339 B=$abc$2385$new_n341 Y=$abc$2385$new_n342
|
||||
.subckt NAND A=$abc$2385$new_n336 B=$abc$2385$new_n342 Y=$abc$2385$new_n343
|
||||
.subckt NAND A=$abc$2385$new_n337 B=$abc$2385$new_n338 Y=$abc$2385$new_n344
|
||||
.subckt AND A=$abc$2385$new_n340 B=$abc$2385$new_n344 Y=$abc$2385$new_n345
|
||||
.subckt ORNOT A=$abc$2385$new_n84 B=in_a_var[1] Y=$abc$2385$new_n85
|
||||
.subckt AND A=$abc$2385$new_n343 B=$abc$2385$new_n345 Y=$abc$2385$new_n346
|
||||
.subckt AND A=in_b_var[0] B=$abc$2385$new_n157 Y=$abc$2385$new_n347
|
||||
.subckt XOR A=in_b_var[1] B=$abc$2385$new_n320 Y=$abc$2385$new_n348
|
||||
.subckt AND A=$abc$2385$new_n342 B=$abc$2385$new_n348 Y=$abc$2385$new_n349
|
||||
.subckt NAND A=$abc$2385$new_n347 B=$abc$2385$new_n349 Y=$abc$2385$new_n350
|
||||
.subckt NAND A=$abc$2385$new_n346 B=$abc$2385$new_n350 Y=$abc$2385$new_n351
|
||||
.subckt NAND A=$abc$2385$new_n335 B=$abc$2385$new_n351 Y=$abc$2385$new_n352
|
||||
.subckt NAND A=$abc$2385$new_n334 B=$abc$2385$new_n352 Y=$abc$2385$new_n353
|
||||
.subckt NAND A=$abc$2385$new_n333 B=$abc$2385$new_n353 Y=$abc$2385$new_n354
|
||||
.subckt NAND A=in_b_var[6] B=$abc$2385$new_n299 Y=$abc$2385$new_n355
|
||||
.subckt XNOR A=:1.test_1[0] B=in_a_var[0] Y=$abc$2385$new_n59
|
||||
.subckt XNOR A=in_a_var[1] B=$abc$2385$new_n84 Y=$abc$2385$new_n86
|
||||
.subckt NAND A=in_b_var[5] B=$abc$2385$new_n302 Y=$abc$2385$new_n356
|
||||
.subckt AND A=$abc$2385$new_n355 B=$abc$2385$new_n356 Y=$abc$2385$new_n357
|
||||
.subckt NAND A=$abc$2385$new_n354 B=$abc$2385$new_n357 Y=$abc$2385$new_n358
|
||||
.subckt AND A=$abc$2385$new_n157 B=$abc$2385$new_n320 Y=$abc$2385$new_n359
|
||||
.subckt ANDNOT A=$abc$2385$new_n359 B=$abc$2385$new_n308 Y=$abc$2385$new_n360
|
||||
.subckt AND A=$abc$2385$new_n305 B=$abc$2385$new_n360 Y=$abc$2385$new_n361
|
||||
.subckt AND A=$abc$2385$new_n303 B=$abc$2385$new_n361 Y=$abc$2385$new_n362
|
||||
.subckt AND A=$abc$2385$new_n302 B=$abc$2385$new_n362 Y=$abc$2385$new_n363
|
||||
.subckt NAND A=$abc$2385$new_n299 B=$abc$2385$new_n363 Y=$abc$2385$new_n364
|
||||
.subckt AND A=$abc$2385$new_n296 B=$abc$2385$new_n298 Y=$abc$2385$new_n365
|
||||
.subckt NAND A=in_b_var[1] B=$abc$2385$new_n86 Y=$abc$2385$new_n87
|
||||
.subckt AND A=$abc$2385$new_n289 B=$abc$2385$new_n292 Y=$abc$2385$new_n366
|
||||
.subckt OR A=:1.test_2[0] B=$abc$2385$new_n75 Y=$abc$2385$new_n367
|
||||
.subckt AND A=$abc$2385$new_n261 B=$abc$2385$new_n367 Y=$abc$2385$new_n368
|
||||
.subckt XNOR A=$abc$2385$new_n270 B=$abc$2385$new_n368 Y=$abc$2385$new_n369
|
||||
.subckt XNOR A=$abc$2385$new_n276 B=$abc$2385$new_n369 Y=$abc$2385$new_n370
|
||||
.subckt ANDNOT A=:1.test_2[2] B=$abc$2385$new_n77 Y=$abc$2385$new_n371
|
||||
.subckt ANDNOT A=:1.test_2[5] B=$abc$2385$new_n91 Y=$abc$2385$new_n372
|
||||
.subckt ANDNOT A=:1.test_2[4] B=$abc$2385$new_n103 Y=$abc$2385$new_n373
|
||||
.subckt XNOR A=$abc$2385$new_n372 B=$abc$2385$new_n373 Y=$abc$2385$new_n374
|
||||
.subckt XNOR A=$abc$2385$new_n371 B=$abc$2385$new_n374 Y=$abc$2385$new_n375
|
||||
.subckt XNOR A=in_b_var[1] B=$abc$2385$new_n86 Y=$abc$2385$new_n88
|
||||
.subckt XOR A=$abc$2385$new_n260 B=$abc$2385$new_n265 Y=$abc$2385$new_n376
|
||||
.subckt XNOR A=$abc$2385$new_n375 B=$abc$2385$new_n376 Y=$abc$2385$new_n377
|
||||
.subckt NAND A=$abc$2385$new_n266 B=$abc$2385$new_n268 Y=$abc$2385$new_n378
|
||||
.subckt ANDNOT A=:1.test_2[7] B=:1.test_1[0] Y=$abc$2385$new_n379
|
||||
.subckt XNOR A=$abc$2385$new_n278 B=$abc$2385$new_n379 Y=$abc$2385$new_n380
|
||||
.subckt XNOR A=$abc$2385$new_n75 B=$abc$2385$new_n380 Y=$abc$2385$new_n381
|
||||
.subckt XNOR A=$abc$2385$new_n378 B=$abc$2385$new_n381 Y=$abc$2385$new_n382
|
||||
.subckt XNOR A=$abc$2385$new_n377 B=$abc$2385$new_n382 Y=$abc$2385$new_n383
|
||||
.subckt XNOR A=$abc$2385$new_n370 B=$abc$2385$new_n383 Y=$abc$2385$new_n384
|
||||
.subckt NAND A=$abc$2385$new_n283 B=$abc$2385$new_n285 Y=$abc$2385$new_n385
|
||||
.subckt ANDNOT A=$abc$2385$new_n62 B=$abc$2385$new_n88 Y=$abc$2385$new_n89
|
||||
.subckt AND A=$abc$2385$new_n272 B=$abc$2385$new_n287 Y=$abc$2385$new_n386
|
||||
.subckt XNOR A=$abc$2385$new_n385 B=$abc$2385$new_n386 Y=$abc$2385$new_n387
|
||||
.subckt XNOR A=$abc$2385$new_n384 B=$abc$2385$new_n387 Y=$abc$2385$new_n388
|
||||
.subckt XNOR A=$abc$2385$new_n366 B=$abc$2385$new_n388 Y=$abc$2385$new_n389
|
||||
.subckt XNOR A=:1.test_2[7] B=$abc$2385$new_n294 Y=$abc$2385$new_n390
|
||||
.subckt XNOR A=$abc$2385$new_n389 B=$abc$2385$new_n390 Y=$abc$2385$new_n391
|
||||
.subckt XNOR A=$abc$2385$new_n365 B=$abc$2385$new_n391 Y=$abc$2385$new_n392
|
||||
.subckt OR A=in_b_var[6] B=$abc$2385$new_n299 Y=$abc$2385$new_n393
|
||||
.subckt ORNOT A=in_b_var[6] B=in_a_var[6] Y=$abc$2385$new_n394
|
||||
.subckt ORNOT A=in_a_var[5] B=in_b_var[5] Y=$abc$2385$new_n395
|
||||
.subckt AND A=$abc$2385$new_n85 B=$abc$2385$new_n87 Y=$abc$2385$new_n90
|
||||
.subckt ORNOT A=in_b_var[5] B=in_a_var[5] Y=$abc$2385$new_n396
|
||||
.subckt ORNOT A=in_b_var[4] B=in_a_var[4] Y=$abc$2385$new_n397
|
||||
.subckt AND A=$abc$2385$new_n396 B=$abc$2385$new_n397 Y=$abc$2385$new_n398
|
||||
.subckt ORNOT A=in_b_var[2] B=in_a_var[2] Y=$abc$2385$new_n399
|
||||
.subckt ORNOT A=in_b_var[3] B=in_a_var[3] Y=$abc$2385$new_n400
|
||||
.subckt NAND A=$abc$2385$new_n399 B=$abc$2385$new_n400 Y=$abc$2385$new_n401
|
||||
.subckt ORNOT A=in_a_var[3] B=in_b_var[3] Y=$abc$2385$new_n402
|
||||
.subckt NAND A=$abc$2385$new_n401 B=$abc$2385$new_n402 Y=$abc$2385$new_n403
|
||||
.subckt ORNOT A=in_a_var[2] B=in_b_var[2] Y=$abc$2385$new_n404
|
||||
.subckt NAND A=$abc$2385$new_n402 B=$abc$2385$new_n404 Y=$abc$2385$new_n405
|
||||
.subckt XNOR A=:1.test_1[2] B=$abc$2385$new_n64 Y=$abc$2385$new_n91
|
||||
.subckt NOR A=$abc$2385$new_n401 B=$abc$2385$new_n405 Y=$abc$2385$new_n406
|
||||
.subckt ORNOT A=in_a_var[0] B=in_b_var[0] Y=$abc$2385$new_n407
|
||||
.subckt ORNOT A=in_a_var[1] B=in_b_var[1] Y=$abc$2385$new_n408
|
||||
.subckt NAND A=$abc$2385$new_n407 B=$abc$2385$new_n408 Y=$abc$2385$new_n409
|
||||
.subckt ORNOT A=in_b_var[1] B=in_a_var[1] Y=$abc$2385$new_n410
|
||||
.subckt NAND A=$abc$2385$new_n409 B=$abc$2385$new_n410 Y=$abc$2385$new_n411
|
||||
.subckt NAND A=$abc$2385$new_n406 B=$abc$2385$new_n411 Y=$abc$2385$new_n412
|
||||
.subckt NAND A=$abc$2385$new_n403 B=$abc$2385$new_n412 Y=$abc$2385$new_n413
|
||||
.subckt ORNOT A=in_a_var[4] B=in_b_var[4] Y=$abc$2385$new_n414
|
||||
.subckt NAND A=$abc$2385$new_n413 B=$abc$2385$new_n414 Y=$abc$2385$new_n415
|
||||
.subckt AND A=$abc$2385$new_n83 B=$abc$2385$new_n91 Y=$abc$2385$new_n92
|
||||
.subckt NAND A=$abc$2385$new_n398 B=$abc$2385$new_n415 Y=$abc$2385$new_n416
|
||||
.subckt NAND A=$abc$2385$new_n395 B=$abc$2385$new_n416 Y=$abc$2385$new_n417
|
||||
.subckt NAND A=$abc$2385$new_n394 B=$abc$2385$new_n417 Y=$abc$2385$new_n418
|
||||
.subckt NAND A=$abc$2385$new_n394 B=$abc$2385$new_n395 Y=$abc$2385$new_n419
|
||||
.subckt NOR A=$abc$2385$new_n409 B=$abc$2385$new_n419 Y=$abc$2385$new_n420
|
||||
.subckt AND A=$abc$2385$new_n398 B=$abc$2385$new_n420 Y=$abc$2385$new_n421
|
||||
.subckt ORNOT A=in_b_var[0] B=in_a_var[0] Y=$abc$2385$new_n422
|
||||
.subckt AND A=$abc$2385$new_n410 B=$abc$2385$new_n414 Y=$abc$2385$new_n423
|
||||
.subckt AND A=$abc$2385$new_n422 B=$abc$2385$new_n423 Y=$abc$2385$new_n424
|
||||
.subckt AND A=$abc$2385$new_n406 B=$abc$2385$new_n424 Y=$abc$2385$new_n425
|
||||
.subckt ORNOT A=$abc$2385$new_n92 B=in_a_var[2] Y=$abc$2385$new_n93
|
||||
.subckt NAND A=$abc$2385$new_n421 B=$abc$2385$new_n425 Y=$abc$2385$new_n426
|
||||
.subckt ORNOT A=in_a_var[6] B=in_b_var[6] Y=$abc$2385$new_n427
|
||||
.subckt AND A=$abc$2385$new_n151 B=$abc$2385$new_n427 Y=$abc$2385$new_n428
|
||||
.subckt AND A=$abc$2385$new_n426 B=$abc$2385$new_n428 Y=$abc$2385$new_n429
|
||||
.subckt AND A=$abc$2385$new_n418 B=$abc$2385$new_n429 Y=$abc$2385$new_n430
|
||||
.subckt AND A=$abc$2385$new_n393 B=$abc$2385$new_n430 Y=$abc$2385$new_n431
|
||||
.subckt AND A=$abc$2385$new_n392 B=$abc$2385$new_n431 Y=$abc$2385$new_n432
|
||||
.subckt AND A=$abc$2385$new_n364 B=$abc$2385$new_n432 Y=$abc$2385$new_n433
|
||||
.subckt AND A=$abc$2385$new_n358 B=$abc$2385$new_n433 Y=$abc$2385$new_n434
|
||||
.subckt AND A=$abc$2385$new_n332 B=$abc$2385$new_n434 Y=$abc$2385$new_n435
|
||||
.subckt XNOR A=in_a_var[2] B=$abc$2385$new_n92 Y=$abc$2385$new_n94
|
||||
.subckt AND A=$abc$2385$new_n157 B=$abc$2385$new_n435 Y=$abc$2385$new_n436
|
||||
.subckt XNOR A=$abc$2385$new_n157 B=$abc$2385$new_n435 Y=$abc$2385$new_n437
|
||||
.subckt ORNOT A=$abc$2385$new_n74 B=:1.test_1[0] Y=$abc$2385$new_n438
|
||||
.subckt MUX A=:1.test_1[0] B=$abc$2385$new_n437 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[0]
|
||||
.subckt ORNOT A=:1.test_1[1] B=$abc$2385$new_n83 Y=$abc$2385$new_n440
|
||||
.subckt XNOR A=$abc$2385$new_n320 B=$abc$2385$new_n436 Y=$abc$2385$new_n441
|
||||
.subckt MUX A=$abc$2385$new_n440 B=$abc$2385$new_n441 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[1]
|
||||
.subckt ORNOT A=:1.test_1[2] B=$abc$2385$new_n83 Y=$abc$2385$new_n443
|
||||
.subckt ANDNOT A=$abc$2385$new_n308 B=$abc$2385$new_n359 Y=$abc$2385$new_n444
|
||||
.subckt XNOR A=$abc$2385$new_n308 B=$abc$2385$new_n359 Y=$abc$2385$new_n445
|
||||
.subckt NAND A=in_b_var[2] B=$abc$2385$new_n94 Y=$abc$2385$new_n95
|
||||
.subckt NAND A=$abc$2385$new_n435 B=$abc$2385$new_n445 Y=$abc$2385$new_n446
|
||||
.subckt ORNOT A=$abc$2385$new_n435 B=$abc$2385$new_n308 Y=$abc$2385$new_n447
|
||||
.subckt AND A=$abc$2385$new_n74 B=$abc$2385$new_n446 Y=$abc$2385$new_n448
|
||||
.subckt NAND A=$abc$2385$new_n447 B=$abc$2385$new_n448 Y=$abc$2385$new_n449
|
||||
.subckt AND A=$abc$2385$new_n443 B=$abc$2385$new_n449 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[2]
|
||||
.subckt ORNOT A=:1.test_1[3] B=$abc$2385$new_n83 Y=$abc$2385$new_n451
|
||||
.subckt AND A=$abc$2385$new_n435 B=$abc$2385$new_n444 Y=$abc$2385$new_n452
|
||||
.subckt AND A=$abc$2385$new_n304 B=$abc$2385$new_n452 Y=$abc$2385$new_n453
|
||||
.subckt XNOR A=$abc$2385$new_n305 B=$abc$2385$new_n452 Y=$abc$2385$new_n454
|
||||
.subckt MUX A=$abc$2385$new_n451 B=$abc$2385$new_n454 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[3]
|
||||
.subckt NAND A=in_b_var[0] B=$abc$2385$new_n59 Y=$abc$2385$new_n60
|
||||
.subckt XNOR A=in_b_var[2] B=$abc$2385$new_n94 Y=$abc$2385$new_n96
|
||||
.subckt ORNOT A=:1.test_1[4] B=$abc$2385$new_n83 Y=$abc$2385$new_n456
|
||||
.subckt ORNOT A=$abc$2385$new_n303 B=$abc$2385$new_n453 Y=$abc$2385$new_n457
|
||||
.subckt XNOR A=$abc$2385$new_n303 B=$abc$2385$new_n453 Y=$abc$2385$new_n458
|
||||
.subckt MUX A=$abc$2385$new_n456 B=$abc$2385$new_n458 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[4]
|
||||
.subckt ORNOT A=:1.test_1[5] B=$abc$2385$new_n83 Y=$abc$2385$new_n460
|
||||
.subckt OR A=$abc$2385$new_n302 B=$abc$2385$new_n457 Y=$abc$2385$new_n461
|
||||
.subckt XOR A=$abc$2385$new_n302 B=$abc$2385$new_n457 Y=$abc$2385$new_n462
|
||||
.subckt NAND A=$abc$2385$new_n74 B=$abc$2385$new_n462 Y=$abc$2385$new_n463
|
||||
.subckt NAND A=$abc$2385$new_n460 B=$abc$2385$new_n463 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[5]
|
||||
.subckt NAND A=$abc$2385$new_n299 B=$abc$2385$new_n461 Y=$abc$2385$new_n465
|
||||
.subckt OR A=$abc$2385$new_n90 B=$abc$2385$new_n96 Y=$abc$2385$new_n97
|
||||
.subckt OR A=$abc$2385$new_n299 B=$abc$2385$new_n461 Y=$abc$2385$new_n466
|
||||
.subckt AND A=$abc$2385$new_n74 B=$abc$2385$new_n466 Y=$abc$2385$new_n467
|
||||
.subckt NAND A=$abc$2385$new_n465 B=$abc$2385$new_n467 Y=$abc$2385$new_n468
|
||||
.subckt MUX A=$abc$2385$new_n73 B=$abc$2385$new_n137 S=$abc$2385$new_n76 Y=$abc$2385$new_n469
|
||||
.subckt OR A=$abc$2385$new_n74 B=$abc$2385$new_n469 Y=$abc$2385$new_n470
|
||||
.subckt NAND A=$abc$2385$new_n468 B=$abc$2385$new_n470 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[6]
|
||||
.subckt NAND A=$abc$2385$new_n392 B=$abc$2385$new_n467 Y=$abc$2385$new_n472
|
||||
.subckt ANDNOT A=$abc$2385$new_n137 B=$abc$2385$new_n76 Y=$abc$2385$new_n473
|
||||
.subckt XNOR A=$abc$2385$new_n150 B=$abc$2385$new_n473 Y=$abc$2385$new_n474
|
||||
.subckt AND A=$abc$2385$new_n472 B=$abc$2385$new_n474 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[7]
|
||||
.subckt XOR A=$abc$2385$new_n90 B=$abc$2385$new_n96 Y=$abc$2385$new_n98
|
||||
.subckt AND A=$abc$2385$new_n58 B=$abc$2385$new_n438 Y=:38.Y[0]
|
||||
.subckt NAND A=in_a_var[1] B=$abc$2385$new_n74 Y=$abc$2385$new_n477
|
||||
.subckt NAND A=$abc$2385$new_n84 B=$abc$2385$new_n477 Y=:38.Y[1]
|
||||
.subckt NAND A=in_a_var[2] B=$abc$2385$new_n74 Y=$abc$2385$new_n479
|
||||
.subckt NAND A=$abc$2385$new_n92 B=$abc$2385$new_n479 Y=:38.Y[2]
|
||||
.subckt NAND A=in_a_var[3] B=$abc$2385$new_n74 Y=$abc$2385$new_n481
|
||||
.subckt NAND A=$abc$2385$new_n104 B=$abc$2385$new_n481 Y=:38.Y[3]
|
||||
.subckt NAND A=in_a_var[4] B=$abc$2385$new_n74 Y=$abc$2385$new_n483
|
||||
.subckt NAND A=$abc$2385$new_n116 B=$abc$2385$new_n483 Y=:38.Y[4]
|
||||
.subckt NAND A=in_a_var[5] B=$abc$2385$new_n74 Y=$abc$2385$new_n485
|
||||
.subckt NAND A=$abc$2385$new_n89 B=$abc$2385$new_n98 Y=$abc$2385$new_n99
|
||||
.subckt NAND A=$abc$2385$new_n127 B=$abc$2385$new_n485 Y=:38.Y[5]
|
||||
.subckt NAND A=in_a_var[6] B=$abc$2385$new_n74 Y=$abc$2385$new_n487
|
||||
.subckt NAND A=$abc$2385$new_n137 B=$abc$2385$new_n487 Y=:38.Y[6]
|
||||
.subckt NAND A=in_a_var[7] B=$abc$2385$new_n74 Y=$abc$2385$new_n489
|
||||
.subckt NAND A=$abc$2385$new_n150 B=$abc$2385$new_n489 Y=:38.Y[7]
|
||||
.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:114:fulladd$252.Y[0] Q=out_var[0]
|
||||
.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.P[1] Q=out_var[1]
|
||||
.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[2] Q=out_var[2]
|
||||
.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[3] Q=out_var[3]
|
||||
.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[4] Q=out_var[4]
|
||||
.subckt XOR A=$abc$2385$new_n89 B=$abc$2385$new_n98 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[2]
|
||||
.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[5] Q=out_var[5]
|
||||
.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[6] Q=out_var[6]
|
||||
.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[7] Q=out_var[7]
|
||||
.subckt DFF C=clk D=:38.Y[0] Q=:1.test_1[0]
|
||||
.subckt DFF C=clk D=:38.Y[1] Q=:1.test_1[1]
|
||||
.subckt DFF C=clk D=:38.Y[2] Q=:1.test_1[2]
|
||||
.subckt DFF C=clk D=:38.Y[3] Q=:1.test_1[3]
|
||||
.subckt DFF C=clk D=:38.Y[4] Q=:1.test_1[4]
|
||||
.subckt DFF C=clk D=:38.Y[5] Q=:1.test_1[5]
|
||||
.subckt DFF C=clk D=:38.Y[6] Q=:1.test_1[6]
|
||||
.subckt NAND A=$abc$2385$new_n97 B=$abc$2385$new_n99 Y=$abc$2385$new_n101
|
||||
.subckt DFF C=clk D=:38.Y[7] Q=:1.test_1[7]
|
||||
.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[0] Q=:1.test_2[0]
|
||||
.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[1] Q=:1.test_2[1]
|
||||
.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[2] Q=:1.test_2[2]
|
||||
.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[3] Q=:1.test_2[3]
|
||||
.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[4] Q=:1.test_2[4]
|
||||
.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[5] Q=:1.test_2[5]
|
||||
.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[6] Q=:1.test_2[6]
|
||||
.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[7] Q=:1.test_2[7]
|
||||
.subckt AND A=$abc$2385$new_n93 B=$abc$2385$new_n95 Y=$abc$2385$new_n102
|
||||
.subckt XNOR A=:1.test_1[3] B=$abc$2385$new_n67 Y=$abc$2385$new_n103
|
||||
.subckt AND A=$abc$2385$new_n83 B=$abc$2385$new_n103 Y=$abc$2385$new_n104
|
||||
.subckt ORNOT A=$abc$2385$new_n104 B=in_a_var[3] Y=$abc$2385$new_n105
|
||||
.subckt XOR A=in_b_var[0] B=$abc$2385$new_n59 Y=$abc$2385$auto$maccmap.cc:114:fulladd$252.Y[0]
|
||||
.subckt XNOR A=in_a_var[3] B=$abc$2385$new_n104 Y=$abc$2385$new_n106
|
||||
.subckt NAND A=in_b_var[3] B=$abc$2385$new_n106 Y=$abc$2385$new_n107
|
||||
.subckt XNOR A=in_b_var[3] B=$abc$2385$new_n106 Y=$abc$2385$new_n108
|
||||
.subckt OR A=$abc$2385$new_n102 B=$abc$2385$new_n108 Y=$abc$2385$new_n109
|
||||
.subckt XOR A=$abc$2385$new_n102 B=$abc$2385$new_n108 Y=$abc$2385$new_n110
|
||||
.subckt NAND A=$abc$2385$new_n101 B=$abc$2385$new_n110 Y=$abc$2385$new_n111
|
||||
.subckt XOR A=$abc$2385$new_n101 B=$abc$2385$new_n110 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[3]
|
||||
.subckt NAND A=$abc$2385$new_n109 B=$abc$2385$new_n111 Y=$abc$2385$new_n113
|
||||
.subckt AND A=$abc$2385$new_n105 B=$abc$2385$new_n107 Y=$abc$2385$new_n114
|
||||
.subckt XNOR A=:1.test_1[4] B=$abc$2385$new_n68 Y=$abc$2385$new_n115
|
||||
.subckt NAND A=$abc$2385$new_n57 B=$abc$2385$new_n60 Y=$abc$2385$new_n62
|
||||
.subckt AND A=$abc$2385$new_n83 B=$abc$2385$new_n115 Y=$abc$2385$new_n116
|
||||
.subckt ORNOT A=$abc$2385$new_n116 B=in_a_var[4] Y=$abc$2385$new_n117
|
||||
.subckt XNOR A=in_a_var[4] B=$abc$2385$new_n116 Y=$abc$2385$new_n118
|
||||
.subckt NAND A=in_b_var[4] B=$abc$2385$new_n118 Y=$abc$2385$new_n119
|
||||
.subckt XNOR A=in_b_var[4] B=$abc$2385$new_n118 Y=$abc$2385$new_n120
|
||||
.subckt OR A=$abc$2385$new_n114 B=$abc$2385$new_n120 Y=$abc$2385$new_n121
|
||||
.subckt XOR A=$abc$2385$new_n114 B=$abc$2385$new_n120 Y=$abc$2385$new_n122
|
||||
.subckt NAND A=$abc$2385$new_n113 B=$abc$2385$new_n122 Y=$abc$2385$new_n123
|
||||
.subckt XOR A=$abc$2385$new_n113 B=$abc$2385$new_n122 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[4]
|
||||
.subckt AND A=$abc$2385$new_n121 B=$abc$2385$new_n123 Y=$abc$2385$new_n125
|
||||
.subckt NOR A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n63
|
||||
.subckt AND A=$abc$2385$new_n117 B=$abc$2385$new_n119 Y=$abc$2385$new_n126
|
||||
.subckt AND A=$abc$2385$new_n77 B=$abc$2385$new_n83 Y=$abc$2385$new_n127
|
||||
.subckt ORNOT A=$abc$2385$new_n127 B=in_a_var[5] Y=$abc$2385$new_n128
|
||||
.subckt XNOR A=in_a_var[5] B=$abc$2385$new_n127 Y=$abc$2385$new_n129
|
||||
.subckt NAND A=in_b_var[5] B=$abc$2385$new_n129 Y=$abc$2385$new_n130
|
||||
.subckt XNOR A=in_b_var[5] B=$abc$2385$new_n129 Y=$abc$2385$new_n131
|
||||
.subckt OR A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n132
|
||||
.subckt NAND A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n133
|
||||
.subckt XOR A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n134
|
||||
.subckt XNOR A=$abc$2385$new_n125 B=$abc$2385$new_n134 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[5]
|
||||
.subckt AND A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n64
|
||||
.subckt AND A=$abc$2385$new_n128 B=$abc$2385$new_n130 Y=$abc$2385$new_n136
|
||||
.subckt AND A=$abc$2385$new_n72 B=$abc$2385$new_n82 Y=$abc$2385$new_n137
|
||||
.subckt ORNOT A=$abc$2385$new_n137 B=in_a_var[6] Y=$abc$2385$new_n138
|
||||
.subckt XNOR A=in_a_var[6] B=$abc$2385$new_n137 Y=$abc$2385$new_n139
|
||||
.subckt NAND A=in_b_var[6] B=$abc$2385$new_n139 Y=$abc$2385$new_n140
|
||||
.subckt XNOR A=in_b_var[6] B=$abc$2385$new_n139 Y=$abc$2385$new_n141
|
||||
.subckt OR A=$abc$2385$new_n136 B=$abc$2385$new_n141 Y=$abc$2385$new_n142
|
||||
.subckt XOR A=$abc$2385$new_n136 B=$abc$2385$new_n141 Y=$abc$2385$new_n143
|
||||
.subckt NAND A=$abc$2385$new_n125 B=$abc$2385$new_n132 Y=$abc$2385$new_n144
|
||||
.subckt AND A=$abc$2385$new_n133 B=$abc$2385$new_n144 Y=$abc$2385$new_n145
|
||||
.subckt XOR A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n65
|
||||
.subckt NAND A=$abc$2385$new_n143 B=$abc$2385$new_n145 Y=$abc$2385$new_n146
|
||||
.subckt XOR A=$abc$2385$new_n143 B=$abc$2385$new_n145 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[6]
|
||||
.subckt AND A=$abc$2385$new_n142 B=$abc$2385$new_n146 Y=$abc$2385$new_n148
|
||||
.subckt AND A=$abc$2385$new_n138 B=$abc$2385$new_n140 Y=$abc$2385$new_n149
|
||||
.subckt AND A=$abc$2385$new_n75 B=$abc$2385$new_n83 Y=$abc$2385$new_n150
|
||||
.subckt NOR A=in_b_var[7] B=in_a_var[7] Y=$abc$2385$new_n151
|
||||
.subckt XOR A=in_b_var[7] B=in_a_var[7] Y=$abc$2385$new_n152
|
||||
.subckt XNOR A=$abc$2385$new_n150 B=$abc$2385$new_n152 Y=$abc$2385$new_n153
|
||||
.subckt XNOR A=$abc$2385$new_n149 B=$abc$2385$new_n153 Y=$abc$2385$new_n154
|
||||
.subckt XNOR A=$abc$2385$new_n148 B=$abc$2385$new_n154 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[7]
|
||||
.gateinit :1.test_2[7]=0
|
||||
.gateinit :1.test_2[6]=0
|
||||
.gateinit :1.test_2[5]=0
|
||||
.gateinit :1.test_2[4]=0
|
||||
.gateinit :1.test_2[3]=0
|
||||
.gateinit :1.test_2[2]=0
|
||||
.gateinit :1.test_2[1]=0
|
||||
.gateinit :1.test_2[0]=0
|
||||
.gateinit :1.test_1[7]=1
|
||||
.gateinit :1.test_1[6]=1
|
||||
.gateinit :1.test_1[5]=1
|
||||
.gateinit :1.test_1[4]=1
|
||||
.gateinit :1.test_1[3]=1
|
||||
.gateinit :1.test_1[2]=1
|
||||
.gateinit :1.test_1[1]=1
|
||||
.gateinit :1.test_1[0]=1
|
||||
.end
|
||||
2
tests/blif/gatesi.ys
Normal file
2
tests/blif/gatesi.ys
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
read_blif gatesi.blif
|
||||
write_blif -gatesi gatesi.blif.out
|
||||
|
|
@ -1,6 +1,11 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
set -e
|
||||
for x in *.ys; do
|
||||
echo "Running $x.."
|
||||
../../yosys -ql ${x%.ys}.log $x
|
||||
../../yosys --no-version -ql ${x%.ys}.log $x
|
||||
done
|
||||
|
||||
for x in *.blif; do
|
||||
diff $x.out $x.ok
|
||||
done
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
|
||||
# run this test many times:
|
||||
# MAKE="make -j8" time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done'
|
||||
|
|
|
|||
1
tests/common-env.sh
Normal file
1
tests/common-env.sh
Normal file
|
|
@ -0,0 +1 @@
|
|||
export YOSYS_MAX_THREADS=4
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
#!/bin/bash
|
||||
source ../common-env.sh
|
||||
|
||||
set -ex
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
|
||||
set -ex
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
|
||||
# run this test many times:
|
||||
# time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done'
|
||||
|
|
|
|||
|
|
@ -43,7 +43,20 @@ def write_vcd(filename: Path, signals: SignalStepMap, timescale='1 ns', date='to
|
|||
if change_time == time:
|
||||
f.write(f"{value} {signal_name}\n")
|
||||
|
||||
def simulate_rosette(rkt_file_path: Path, vcd_path: Path, num_steps: int, rnd: Random):
|
||||
|
||||
def simulate_rosette(
|
||||
rkt_file_path: Path,
|
||||
vcd_path: Path,
|
||||
num_steps: int,
|
||||
rnd: Random,
|
||||
use_assoc_list_helpers: bool = False,
|
||||
):
|
||||
"""
|
||||
Args:
|
||||
- use_assoc_list_helpers: If True, will use the association list helpers
|
||||
in the Racket file. The file should have been generated with the
|
||||
-assoc-list-helpers flag in the yosys command.
|
||||
"""
|
||||
signals: dict[str, list[str]] = {}
|
||||
inputs: SignalWidthMap = {}
|
||||
outputs: SignalWidthMap = {}
|
||||
|
|
@ -83,12 +96,32 @@ def simulate_rosette(rkt_file_path: Path, vcd_path: Path, num_steps: int, rnd: R
|
|||
for step in range(num_steps):
|
||||
this_step = f"step_{step}"
|
||||
value_list: list[str] = []
|
||||
for signal, width in inputs.items():
|
||||
value = signals[signal][step]
|
||||
value_list.append(f"(bv #b{value} {width})")
|
||||
gold_Inputs = f"(gold_Inputs {' '.join(value_list)})"
|
||||
if use_assoc_list_helpers:
|
||||
# Generate inputs as a list of cons pairs making up the
|
||||
# association list.
|
||||
for signal, width in inputs.items():
|
||||
value = signals[signal][step]
|
||||
value_list.append(f'(cons "{signal}" (bv #b{value} {width}))')
|
||||
else:
|
||||
# Otherwise, we generate the inputs as a list of bitvectors.
|
||||
for signal, width in inputs.items():
|
||||
value = signals[signal][step]
|
||||
value_list.append(f"(bv #b{value} {width})")
|
||||
gold_Inputs = (
|
||||
f"(gold_inputs_helper (list {' '.join(value_list)}))"
|
||||
if use_assoc_list_helpers
|
||||
else f"(gold_Inputs {' '.join(value_list)})"
|
||||
)
|
||||
gold_State = f"(cdr step_{step-1})" if step else "gold_initial"
|
||||
test_rkt_file.write(f"(define {this_step} (gold {gold_Inputs} {gold_State})) (car {this_step})\n")
|
||||
get_value_expr = (
|
||||
f"(gold_outputs_helper (car {this_step}))"
|
||||
if use_assoc_list_helpers
|
||||
else f"(car {this_step})"
|
||||
)
|
||||
test_rkt_file.write(
|
||||
f"(define {this_step} (gold {gold_Inputs} {gold_State})) {get_value_expr}\n"
|
||||
)
|
||||
|
||||
|
||||
cmd = ["racket", test_rkt_file_path]
|
||||
status = subprocess.run(cmd, capture_output=True)
|
||||
|
|
@ -98,9 +131,23 @@ def simulate_rosette(rkt_file_path: Path, vcd_path: Path, num_steps: int, rnd: R
|
|||
signals[signal] = []
|
||||
|
||||
for line in status.stdout.decode().splitlines():
|
||||
m = re.match(r'\(gold_Outputs( \(bv \S+ \d+\))+\)', line)
|
||||
m = (
|
||||
re.match(r"\(list( \(cons \"\S+\" \(bv \S+ \d+\)\))+\)", line)
|
||||
if use_assoc_list_helpers
|
||||
else re.match(r"\(gold_Outputs( \(bv \S+ \d+\))+\)", line)
|
||||
)
|
||||
assert m, f"Incomplete output definition {line!r}"
|
||||
for output, (value, width) in zip(outputs.keys(), re.findall(r'\(bv (\S+) (\d+)\)', line)):
|
||||
outputs_values_and_widths = (
|
||||
{
|
||||
output: re.findall(
|
||||
r"\(cons \"" + output + r"\" \(bv (\S+) (\d+)\)\)", line
|
||||
)[0]
|
||||
for output in outputs.keys()
|
||||
}.items()
|
||||
if use_assoc_list_helpers
|
||||
else zip(outputs.keys(), re.findall(r"\(bv (\S+) (\d+)\)", line))
|
||||
)
|
||||
for output, (value, width) in outputs_values_and_widths:
|
||||
assert isinstance(value, str), f"Bad value {value!r}"
|
||||
assert value.startswith(('#b', '#x')), f"Non-binary value {value!r}"
|
||||
assert int(width) == outputs[output], f"Width mismatch for output {output!r} (got {width}, expected {outputs[output]})"
|
||||
|
|
|
|||
|
|
@ -1,2 +1,6 @@
|
|||
#!/usr/bin/env bash
|
||||
pytest -v -m "not smt and not rkt" "$@"
|
||||
source ../common-env.sh
|
||||
|
||||
SCRIPT_DIR=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd )
|
||||
|
||||
pytest -v -m "not smt and not rkt" "$SCRIPT_DIR" "$@"
|
||||
|
|
|
|||
|
|
@ -74,7 +74,8 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd):
|
|||
yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
|
||||
|
||||
@pytest.mark.rkt
|
||||
def test_rkt(cell, parameters, tmp_path, num_steps, rnd):
|
||||
@pytest.mark.parametrize("use_assoc_list_helpers", [True, False])
|
||||
def test_rkt(cell, parameters, tmp_path, num_steps, rnd, use_assoc_list_helpers):
|
||||
import rkt_vcd
|
||||
|
||||
rtlil_file = tmp_path / 'rtlil.il'
|
||||
|
|
@ -83,8 +84,9 @@ def test_rkt(cell, parameters, tmp_path, num_steps, rnd):
|
|||
vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
|
||||
|
||||
cell.write_rtlil_file(rtlil_file, parameters)
|
||||
yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_rosette -provides {quote(rkt_file)}")
|
||||
rkt_vcd.simulate_rosette(rkt_file, vcd_functional_file, num_steps, rnd(cell.name + "-rkt"))
|
||||
use_assoc_helpers_flag = '-assoc-list-helpers' if use_assoc_list_helpers else ''
|
||||
yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_rosette -provides {use_assoc_helpers_flag} {quote(rkt_file)}")
|
||||
rkt_vcd.simulate_rosette(rkt_file, vcd_functional_file, num_steps, rnd(cell.name + "-rkt"), use_assoc_list_helpers=use_assoc_list_helpers)
|
||||
yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
|
||||
|
||||
def test_print_graph(tmp_path):
|
||||
|
|
|
|||
190
tests/functional/test_smtbmc_witness_mismatch.py
Normal file
190
tests/functional/test_smtbmc_witness_mismatch.py
Normal file
|
|
@ -0,0 +1,190 @@
|
|||
import json
|
||||
import shutil
|
||||
import subprocess
|
||||
from pathlib import Path
|
||||
|
||||
import pytest
|
||||
|
||||
base_path = Path(__file__).resolve().parent.parent.parent
|
||||
|
||||
pytestmark = pytest.mark.skipif(shutil.which("z3") is None, reason="z3 not available")
|
||||
|
||||
def run(cmd, **kwargs):
|
||||
"""Run a command and assert it succeeds."""
|
||||
status = subprocess.run(cmd, **kwargs)
|
||||
assert status.returncode == 0, f"{cmd[0]} failed"
|
||||
return status
|
||||
|
||||
|
||||
def write_smt2(tmp_path, verilog_text):
|
||||
"""Write Verilog to temp and emit SMT2 via yosys."""
|
||||
vfile = tmp_path / "design.v"
|
||||
smt2 = tmp_path / "design.smt2"
|
||||
vfile.write_text(verilog_text)
|
||||
run([base_path / "yosys", "-Q", "-p",
|
||||
f"read_verilog {vfile}; prep -top top; write_smt2 {smt2}"])
|
||||
return smt2
|
||||
|
||||
|
||||
def witness_entries(smt2_path):
|
||||
"""Parse yosys-smt2-witness JSON records from an SMT2 file."""
|
||||
entries = []
|
||||
marker = "yosys-smt2-witness"
|
||||
with open(smt2_path, "r") as f:
|
||||
for line in f:
|
||||
if marker not in line:
|
||||
continue
|
||||
payload = line.split(marker, 1)[1].strip()
|
||||
entries.append(json.loads(payload))
|
||||
return entries
|
||||
|
||||
|
||||
def find_entry(entries, entry_type):
|
||||
"""Return the first witness entry of the given type."""
|
||||
for entry in entries:
|
||||
if entry.get("type") == entry_type:
|
||||
return entry
|
||||
return None
|
||||
|
||||
|
||||
def write_yw(yw_path, signals, bits):
|
||||
"""Write a minimal Yosys witness file with one step of bits."""
|
||||
data = {
|
||||
"format": "Yosys Witness Trace",
|
||||
"clocks": [],
|
||||
"signals": signals,
|
||||
"steps": [{"bits": bits}],
|
||||
}
|
||||
yw_path.write_text(json.dumps(data))
|
||||
|
||||
|
||||
def run_smtbmc(smt2_path, yw_path):
|
||||
"""Run yosys-smtbmc on the SMT2 file with a witness trace."""
|
||||
cmd = [
|
||||
base_path / "yosys-smtbmc",
|
||||
"-s", "z3",
|
||||
"-m", "top",
|
||||
"--check-witness",
|
||||
"--yw", yw_path,
|
||||
"-t", "1",
|
||||
smt2_path,
|
||||
]
|
||||
return subprocess.run(cmd, capture_output=True, text=True)
|
||||
|
||||
|
||||
def assert_no_mismatch_message(result):
|
||||
"""Assert the mismatch error prefix is absent from outputs."""
|
||||
combined = (result.stderr or "") + (result.stdout or "")
|
||||
assert "Yosys witness signal mismatch" not in combined
|
||||
|
||||
|
||||
def assert_has_mismatch_message(result, msg):
|
||||
"""Assert the mismatch error prefix and substring are present."""
|
||||
combined = (result.stderr or "") + (result.stdout or "")
|
||||
assert "Yosys witness signal mismatch" in combined
|
||||
assert msg in combined
|
||||
|
||||
|
||||
def test_missing_signal_path(tmp_path):
|
||||
smt2 = write_smt2(tmp_path, "module top(input ok, output out); assign out = ok; endmodule")
|
||||
yw_path = tmp_path / "trace.yw"
|
||||
signals = [{"path": ["\\missing"], "offset": 0, "width": 1, "init_only": False}]
|
||||
write_yw(yw_path, signals, "1")
|
||||
result = run_smtbmc(smt2, yw_path)
|
||||
assert result.returncode != 0
|
||||
assert_has_mismatch_message(result, "signal not found in design")
|
||||
|
||||
|
||||
def test_width_mismatch(tmp_path):
|
||||
smt2 = write_smt2(tmp_path, "module top(input ok, output out); assign out = ok; endmodule")
|
||||
entries = witness_entries(smt2)
|
||||
input_entry = find_entry(entries, "input")
|
||||
assert input_entry is not None
|
||||
yw_path = tmp_path / "trace.yw"
|
||||
signals = [{
|
||||
"path": input_entry["path"],
|
||||
"offset": 0,
|
||||
"width": 2,
|
||||
"init_only": False,
|
||||
}]
|
||||
write_yw(yw_path, signals, "10")
|
||||
result = run_smtbmc(smt2, yw_path)
|
||||
assert result.returncode != 0
|
||||
assert_has_mismatch_message(result, "signal width/offset mismatch")
|
||||
|
||||
|
||||
def test_memory_address_oob(tmp_path):
|
||||
verilog = """
|
||||
module top(input ok, output [7:0] mem_out);
|
||||
reg [7:0] mem [0:1];
|
||||
assign mem_out = mem[0] ^ {8{ok}};
|
||||
endmodule
|
||||
"""
|
||||
smt2 = write_smt2(tmp_path, verilog)
|
||||
entries = witness_entries(smt2)
|
||||
mem_entry = find_entry(entries, "mem")
|
||||
assert mem_entry is not None
|
||||
addr = mem_entry["size"]
|
||||
yw_path = tmp_path / "trace.yw"
|
||||
signals = [{
|
||||
"path": mem_entry["path"] + [f"\\[{addr}]"],
|
||||
"offset": 0,
|
||||
"width": mem_entry["width"],
|
||||
"init_only": False,
|
||||
}]
|
||||
bits = "0" * mem_entry["width"]
|
||||
write_yw(yw_path, signals, bits)
|
||||
result = run_smtbmc(smt2, yw_path)
|
||||
assert result.returncode != 0
|
||||
assert_has_mismatch_message(result, "memory address out of bounds")
|
||||
|
||||
|
||||
def test_allowed_extra_signal_in_design(tmp_path):
|
||||
verilog = """
|
||||
module top(input ok, input extra, output [1:0] out);
|
||||
assign out = {ok, extra};
|
||||
endmodule
|
||||
"""
|
||||
smt2 = write_smt2(tmp_path, verilog)
|
||||
entries = witness_entries(smt2)
|
||||
input_entry = find_entry(entries, "input")
|
||||
assert input_entry is not None
|
||||
yw_path = tmp_path / "trace.yw"
|
||||
signals = [{
|
||||
"path": input_entry["path"],
|
||||
"offset": 0,
|
||||
"width": input_entry["width"],
|
||||
"init_only": False,
|
||||
}]
|
||||
bits = "0" * input_entry["width"]
|
||||
write_yw(yw_path, signals, bits)
|
||||
result = run_smtbmc(smt2, yw_path)
|
||||
# With --check-witness and no assertions, smtbmc can still exit non-zero.
|
||||
# Thus we don't check the result.returncode here and in the other success
|
||||
# cases.
|
||||
assert_no_mismatch_message(result)
|
||||
|
||||
|
||||
def test_allowed_extra_memory_in_design(tmp_path):
|
||||
verilog = """
|
||||
module top(input ok, output [7:0] out);
|
||||
reg [7:0] mem0 [0:1];
|
||||
reg [7:0] mem1 [0:3];
|
||||
assign out = mem0[0] ^ mem1[0];
|
||||
endmodule
|
||||
"""
|
||||
smt2 = write_smt2(tmp_path, verilog)
|
||||
entries = witness_entries(smt2)
|
||||
input_entry = find_entry(entries, "input")
|
||||
assert input_entry is not None
|
||||
yw_path = tmp_path / "trace.yw"
|
||||
signals = [{
|
||||
"path": input_entry["path"],
|
||||
"offset": 0,
|
||||
"width": input_entry["width"],
|
||||
"init_only": False,
|
||||
}]
|
||||
bits = "1" * input_entry["width"]
|
||||
write_yw(yw_path, signals, bits)
|
||||
result = run_smtbmc(smt2, yw_path)
|
||||
assert_no_mismatch_message(result)
|
||||
|
|
@ -9,7 +9,7 @@ generate_target() {
|
|||
echo "all: $target_name"
|
||||
echo ".PHONY: $target_name"
|
||||
echo "$target_name:"
|
||||
printf "\t@%s\n" "$test_command"
|
||||
printf "\t@YOSYS_MAX_THREADS=4 %s\n" "$test_command"
|
||||
printf "\t@echo 'Passed %s'\n" "$target_name"
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
|
||||
OPTIND=1
|
||||
seed="" # default to no seed specified
|
||||
|
|
|
|||
|
|
@ -5,8 +5,9 @@ module dff (D, CLK, Q);
|
|||
output Q;
|
||||
assign Q = IQ; // IQ
|
||||
always @(posedge CLK) begin
|
||||
// "(D)"
|
||||
IQ <= D;
|
||||
end
|
||||
always @(posedge CLK) begin
|
||||
IQN <= ~(D);
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@ module imux2 (A, B, S, Y);
|
|||
endmodule
|
||||
module dff (D, CLK, RESET, PRESET, Q, QN);
|
||||
reg IQ, IQN;
|
||||
wire IQ_clear, IQ_preset;
|
||||
input D;
|
||||
input CLK;
|
||||
input RESET;
|
||||
|
|
@ -49,25 +50,30 @@ module dff (D, CLK, RESET, PRESET, Q, QN);
|
|||
assign Q = IQ; // "IQ"
|
||||
output QN;
|
||||
assign QN = IQN; // "IQN"
|
||||
always @(posedge CLK, posedge RESET, posedge PRESET) begin
|
||||
if ((RESET) && (PRESET)) begin
|
||||
always @(posedge CLK, posedge IQ_clear, posedge IQ_preset) begin
|
||||
if (IQ_clear) begin
|
||||
IQ <= 0;
|
||||
IQN <= 0;
|
||||
end
|
||||
else if (RESET) begin
|
||||
IQ <= 0;
|
||||
IQN <= 1;
|
||||
end
|
||||
else if (PRESET) begin
|
||||
else if (IQ_preset) begin
|
||||
IQ <= 1;
|
||||
IQN <= 0;
|
||||
end
|
||||
else begin
|
||||
// "D"
|
||||
IQ <= D;
|
||||
end
|
||||
end
|
||||
always @(posedge CLK, posedge IQ_clear, posedge IQ_preset) begin
|
||||
if (IQ_preset) begin
|
||||
IQN <= 0;
|
||||
end
|
||||
else if (IQ_clear) begin
|
||||
IQN <= 1;
|
||||
end
|
||||
else begin
|
||||
IQN <= ~(D);
|
||||
end
|
||||
end
|
||||
assign IQ_clear = RESET;
|
||||
assign IQ_preset = PRESET;
|
||||
endmodule
|
||||
module latch (D, G, Q, QN);
|
||||
reg IQ, IQN;
|
||||
|
|
|
|||
9
tests/liberty/read_liberty.ys
Normal file
9
tests/liberty/read_liberty.ys
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
read_liberty retention.lib
|
||||
rename retention_cell retention_cell_lib
|
||||
read_verilog retention.lib.verilogsim
|
||||
proc
|
||||
rename retention_cell retention_cell_vlog
|
||||
async2sync
|
||||
equiv_make retention_cell_lib retention_cell_vlog equiv
|
||||
equiv_induct equiv
|
||||
equiv_status -assert equiv
|
||||
57
tests/liberty/retention.lib
Normal file
57
tests/liberty/retention.lib
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
library (retention) {
|
||||
delay_model : table_lookup;
|
||||
voltage_unit : 1V;
|
||||
current_unit : 1mA;
|
||||
leakage_power_unit : 1nW;
|
||||
time_unit : 1ns;
|
||||
capacitive_load_unit (1, pf);
|
||||
pulling_resistance_unit : 1kohm;
|
||||
input_threshold_pct_rise : 50;
|
||||
input_threshold_pct_fall : 50;
|
||||
output_threshold_pct_rise : 50;
|
||||
output_threshold_pct_fall : 50;
|
||||
slew_lower_threshold_pct_rise : 30;
|
||||
slew_upper_threshold_pct_rise : 70;
|
||||
slew_upper_threshold_pct_fall : 70;
|
||||
slew_lower_threshold_pct_fall : 30;
|
||||
cell ("retention_cell") {
|
||||
ff (Q1,QN1) {
|
||||
clocked_on : "CK";
|
||||
next_state : "(D * !SE + SI * SE)";
|
||||
clear : "(((!B2B) * !Q2) + !RD)";
|
||||
preset : "((!B2B) * Q2)";
|
||||
clear_preset_var1 : "L";
|
||||
clear_preset_var2 : "H";
|
||||
}
|
||||
latch (Q2,QN2) {
|
||||
enable : "B1";
|
||||
data_in : "Q1";
|
||||
}
|
||||
pin (B1) {
|
||||
direction : input;
|
||||
}
|
||||
pin (B2B) {
|
||||
direction : input;
|
||||
}
|
||||
pin (CK) {
|
||||
clock : true;
|
||||
direction : input;
|
||||
}
|
||||
pin (D) {
|
||||
direction : input;
|
||||
}
|
||||
pin (Q) {
|
||||
direction : output;
|
||||
function : "Q1";
|
||||
}
|
||||
pin (RD) {
|
||||
direction : input;
|
||||
}
|
||||
pin (SE) {
|
||||
direction : input;
|
||||
}
|
||||
pin (SI) {
|
||||
direction : input;
|
||||
}
|
||||
}
|
||||
}
|
||||
42
tests/liberty/retention.lib.filtered.ok
Normal file
42
tests/liberty/retention.lib.filtered.ok
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
library(retention) {
|
||||
cell("retention_cell") {
|
||||
ff(Q1, QN1) {
|
||||
clocked_on : "CK" ;
|
||||
next_state : "(D * !SE + SI * SE)" ;
|
||||
clear : "(((!B2B) * !Q2) + !RD)" ;
|
||||
preset : "((!B2B) * Q2)" ;
|
||||
clear_preset_var1 : "L" ;
|
||||
clear_preset_var2 : "H" ;
|
||||
}
|
||||
latch(Q2, QN2) {
|
||||
enable : "B1" ;
|
||||
data_in : "Q1" ;
|
||||
}
|
||||
pin(B1) {
|
||||
direction : input ;
|
||||
}
|
||||
pin(B2B) {
|
||||
direction : input ;
|
||||
}
|
||||
pin(CK) {
|
||||
clock : true ;
|
||||
direction : input ;
|
||||
}
|
||||
pin(D) {
|
||||
direction : input ;
|
||||
}
|
||||
pin(Q) {
|
||||
direction : output ;
|
||||
function : "Q1" ;
|
||||
}
|
||||
pin(RD) {
|
||||
direction : input ;
|
||||
}
|
||||
pin(SE) {
|
||||
direction : input ;
|
||||
}
|
||||
pin(SI) {
|
||||
direction : input ;
|
||||
}
|
||||
}
|
||||
}
|
||||
44
tests/liberty/retention.lib.verilogsim.ok
Normal file
44
tests/liberty/retention.lib.verilogsim.ok
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
module retention_cell (B1, B2B, CK, D, Q, RD, SE, SI);
|
||||
reg Q1, QN1;
|
||||
wire Q1_clear, Q1_preset;
|
||||
reg Q2, QN2;
|
||||
input B1;
|
||||
input B2B;
|
||||
input CK;
|
||||
input D;
|
||||
output Q;
|
||||
assign Q = Q1; // "Q1"
|
||||
input RD;
|
||||
input SE;
|
||||
input SI;
|
||||
always @(posedge CK, posedge Q1_clear, posedge Q1_preset) begin
|
||||
if (Q1_clear) begin
|
||||
Q1 <= 0;
|
||||
end
|
||||
else if (Q1_preset) begin
|
||||
Q1 <= 1;
|
||||
end
|
||||
else begin
|
||||
Q1 <= ((D&(~SE))|(SI&SE));
|
||||
end
|
||||
end
|
||||
always @(posedge CK, posedge Q1_clear, posedge Q1_preset) begin
|
||||
if (Q1_clear) begin
|
||||
QN1 <= 1;
|
||||
end
|
||||
else if (Q1_preset) begin
|
||||
QN1 <= 0;
|
||||
end
|
||||
else begin
|
||||
QN1 <= ~(((D&(~SE))|(SI&SE)));
|
||||
end
|
||||
end
|
||||
assign Q1_clear = (((~B2B)&(~Q2))|(~RD));
|
||||
assign Q1_preset = ((~B2B)&Q2);
|
||||
always @* begin
|
||||
if (B1) begin
|
||||
Q2 <= Q1;
|
||||
QN2 <= ~(Q1);
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
set -eo pipefail
|
||||
|
||||
for x in *.lib; do
|
||||
|
|
|
|||
|
|
@ -4,8 +4,9 @@ module DFF (D, CK, Q);
|
|||
input CK;
|
||||
output Q;
|
||||
always @(posedge CK) begin
|
||||
// "D"
|
||||
IQ <= D;
|
||||
end
|
||||
always @(posedge CK) begin
|
||||
IQN <= ~(D);
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -5,8 +5,9 @@ module dff1 (D, CLK, Q);
|
|||
output Q;
|
||||
assign Q = IQ; // IQ
|
||||
always @(posedge CLK) begin
|
||||
// !D
|
||||
IQ <= (~D);
|
||||
end
|
||||
always @(posedge CLK) begin
|
||||
IQN <= ~((~D));
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -17,8 +18,9 @@ module dff2 (D, CLK, Q);
|
|||
output Q;
|
||||
assign Q = IQ; // "IQ"
|
||||
always @(posedge CLK) begin
|
||||
// D '
|
||||
IQ <= (~D);
|
||||
end
|
||||
always @(posedge CLK) begin
|
||||
IQN <= ~((~D));
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -32,8 +34,9 @@ module dffe (D, EN, CLK, Q, QN);
|
|||
output QN;
|
||||
assign QN = IQN; // "IQN"
|
||||
always @(negedge CLK) begin
|
||||
// ( D & EN ) | ( IQ & ! EN )
|
||||
IQ <= ((D&EN)|(IQ&(~EN)));
|
||||
end
|
||||
always @(negedge CLK) begin
|
||||
IQN <= ~(((D&EN)|(IQ&(~EN))));
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
|
||||
set -e
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
set -eu
|
||||
|
||||
OPTIND=1
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
|
||||
set -e
|
||||
|
||||
|
|
|
|||
1246
tests/opt/opt_balance_tree.ys
Normal file
1246
tests/opt/opt_balance_tree.ys
Normal file
File diff suppressed because it is too large
Load diff
10
tests/opt/opt_clean_standalone_wires.ys
Normal file
10
tests/opt/opt_clean_standalone_wires.ys
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
read_rtlil << EOT
|
||||
module \test
|
||||
wire \wire_a
|
||||
wire \wire_f
|
||||
connect \wire_f \wire_a
|
||||
end
|
||||
EOT
|
||||
|
||||
opt_clean
|
||||
select -assert-count 0 */*
|
||||
|
|
@ -319,3 +319,59 @@ check
|
|||
equiv_opt -assert opt_expr -keepdc
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$mul r:A_WIDTH=4 %i r:B_WIDTH=4 %i r:Y_WIDTH=8 %i
|
||||
|
||||
###########
|
||||
|
||||
design -reset
|
||||
read_rtlil <<EOF
|
||||
module \top
|
||||
wire width 3 input 2 \binary
|
||||
|
||||
wire width 32 output 3 \y
|
||||
|
||||
cell $pow $0
|
||||
parameter \A_WIDTH 32
|
||||
parameter \B_WIDTH 3
|
||||
parameter \A_SIGNED 1
|
||||
parameter \B_SIGNED 0
|
||||
parameter \Y_WIDTH 32
|
||||
connect \A 2
|
||||
connect \B \binary
|
||||
connect \Y \y
|
||||
end
|
||||
end
|
||||
EOF
|
||||
|
||||
scratchpad -set opt.did_something false
|
||||
opt_expr
|
||||
scratchpad -assert opt.did_something true
|
||||
sat -verify -set binary 0 -prove y 1
|
||||
sat -verify -set binary 1 -prove y 2
|
||||
sat -verify -set binary 2 -prove y 4
|
||||
sat -verify -set binary 3 -prove y 8
|
||||
|
||||
###########
|
||||
|
||||
design -reset
|
||||
read_rtlil <<EOF
|
||||
module \top
|
||||
wire width 3 input 2 \binary
|
||||
|
||||
wire width 32 output 3 \y
|
||||
|
||||
cell $pow $0
|
||||
parameter \A_WIDTH 2
|
||||
parameter \B_WIDTH 3
|
||||
parameter \A_SIGNED 1
|
||||
parameter \B_SIGNED 0
|
||||
parameter \Y_WIDTH 32
|
||||
connect \A 2'10
|
||||
connect \B \binary
|
||||
connect \Y \y
|
||||
end
|
||||
end
|
||||
EOF
|
||||
|
||||
scratchpad -set opt.did_something false
|
||||
opt_expr
|
||||
scratchpad -assert opt.did_something false
|
||||
|
|
@ -1,11 +1,12 @@
|
|||
read_verilog -sv <<EOT
|
||||
module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
|
||||
wire[8:0] a = 8'b0;
|
||||
wire[8:0] a;
|
||||
initial begin
|
||||
a = 8'b0;
|
||||
a |= i;
|
||||
a |= j;
|
||||
end
|
||||
assign o = a;
|
||||
assign o = a;
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
|
|
@ -17,12 +18,13 @@ select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
|
|||
design -reset
|
||||
read_verilog -sv <<EOT
|
||||
module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
|
||||
wire[8:0] a = 8'b0;
|
||||
wire[8:0] a;
|
||||
initial begin
|
||||
a += i;
|
||||
a += j;
|
||||
a = 8'b0;
|
||||
a += i;
|
||||
a += j;
|
||||
end
|
||||
assign o = a;
|
||||
assign o = a;
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
|
|
@ -34,12 +36,13 @@ select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
|
|||
design -reset
|
||||
read_verilog -sv <<EOT
|
||||
module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
|
||||
wire[8:0] a = 8'b0;
|
||||
wire[8:0] a;
|
||||
initial begin
|
||||
a ^= i;
|
||||
a ^= j;
|
||||
a = 8'b0;
|
||||
a ^= i;
|
||||
a ^= j;
|
||||
end
|
||||
assign o = a;
|
||||
assign o = a;
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
|
|
@ -51,12 +54,13 @@ select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
|
|||
design -reset
|
||||
read_verilog -sv <<EOT
|
||||
module opt_expr_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
|
||||
wire[8:0] a = 8'b0;
|
||||
wire[8:0] a;
|
||||
initial begin
|
||||
a -= i;
|
||||
a -= j;
|
||||
a = 8'b0;
|
||||
a -= i;
|
||||
a -= j;
|
||||
end
|
||||
assign o = a;
|
||||
assign o = a;
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
|
|
@ -68,12 +72,13 @@ select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
|
|||
design -reset
|
||||
read_verilog -sv <<EOT
|
||||
module opt_expr_and_test(input [3:0] i, input [7:0] j, output [8:0] o);
|
||||
wire[8:0] a = 8'b11111111;
|
||||
wire[8:0] a;
|
||||
initial begin
|
||||
a &= i;
|
||||
a &= j;
|
||||
a = 8'b11111111;
|
||||
a &= i;
|
||||
a &= j;
|
||||
end
|
||||
assign o = a;
|
||||
assign o = a;
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
|
|
|
|||
16
tests/opt/opt_merge_properties.ys
Normal file
16
tests/opt/opt_merge_properties.ys
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
read_verilog -sv <<EOF
|
||||
module top ();
|
||||
always_comb begin
|
||||
label1: cover(0);
|
||||
label2: cover(0);
|
||||
end
|
||||
endmodule
|
||||
EOF
|
||||
|
||||
hierarchy -top top
|
||||
proc
|
||||
chformal -lower
|
||||
clean
|
||||
opt_merge
|
||||
select -assert-count 2 t:$cover
|
||||
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
|
||||
# run this test many times:
|
||||
# time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done'
|
||||
|
|
|
|||
106
tests/pass-fuzzing.md
Normal file
106
tests/pass-fuzzing.md
Normal file
|
|
@ -0,0 +1,106 @@
|
|||
Suppose you're making significant changes to a pass that should not change
|
||||
the pass's output in any way. It might be useful to run a large number of
|
||||
automatically generated tests to try to find bugs where the output has
|
||||
changed. This document describes how to do that.
|
||||
|
||||
Basically we're going to use [AFL++](https://github.com/AFLplusplus/AFLplusplus) with the
|
||||
[Grammar-Mutator](https://github.com/AFLplusplus/Grammar-Mutator) plugin to generate
|
||||
RTLIL testcases. For each testcase, we run a Yosys script that applies both the old and new
|
||||
implementation of the pass to the same design and compares the results. Testcase
|
||||
generation is coverage-guided, i.e. the fuzzer will try to find testcases that exercise all
|
||||
code in the old and new implementation of the pass (and in the RTLIL parser).
|
||||
|
||||
## Setup
|
||||
|
||||
These instructions clone tools into subdirectories of your home directory. They assume
|
||||
you have a Yosys checkout under `$HOME/yosys`, and that you're testing the `opt_merge` pass.
|
||||
They have been tested with AFL++ revision 68b492b2c7725816068718ef9437b72b40e67519 and Grammar-Mutator revision 05d8f537f8d656f0754e7ad5dcc653c42cb4f8ff.
|
||||
|
||||
Clone and build AFL++ and Grammar-Mutator:
|
||||
```
|
||||
cd $HOME
|
||||
git clone https://github.com/AFLplusplus/AFLplusplus.git
|
||||
git -C AFLplusplus checkout stable
|
||||
git clone https://github.com/AFLplusplus/Grammar-Mutator.git
|
||||
git -C Grammar-Mutator checkout stable
|
||||
```
|
||||
|
||||
Check that `rtlil-fuzz-grammar.json` generates RTLIL constructs relevant to your pass.
|
||||
Currently it's quite simple and generates a limited set of cells and wires; you may need to
|
||||
extend it to generate different kinds of cells and other RTLIL constructs (e.g. `proc`).
|
||||
|
||||
Build AFL++ and Grammar-Mutator:
|
||||
```
|
||||
make -C $HOME/AFLplusplus -j all
|
||||
make -C $HOME/Grammar-Mutator -j GRAMMAR_FILE=$HOME/yosys/tests/tools/rtlil-fuzz-grammar.json
|
||||
```
|
||||
|
||||
Create a Yosys commit that adds the old version of your pass as a new command, e.g. copy
|
||||
`opt_merge.cc` into `old_opt_merge.cc` and change the name of the command to `old_opt_merge`.
|
||||
[Here's](https://github.com/YosysHQ/yosys/commit/827cd8c998f3e455b14ac990a3159030ddc19b21) an example.
|
||||
|
||||
You may also need to patch in [this commit](https://github.com/YosysHQ/yosys/commit/121c52f514c4ca282b4e6b3b14f71184f3849ddf) to work around a bug involving `std::reverse` on
|
||||
empty vectors in the RTLIL parser when building with fuzzing instrumentation.
|
||||
I think this is a clang++ bug so hopefully it will get fixed eventually and that patch will not be
|
||||
necessary.
|
||||
|
||||
Rebuild Yosys with the AFL++ compiler wrapper. This assumes your config builds Yosys with clang++.
|
||||
```
|
||||
(cd $HOME/yosys; patch -lp1 << EOF)
|
||||
diff --git a/Makefile b/Makefile
|
||||
index 9c361294d..c9a98f74c 100644
|
||||
--- a/Makefile
|
||||
+++ b/Makefile
|
||||
@@ -238,7 +238,7 @@
|
||||
LTOFLAGS := $(GCC_LTO)
|
||||
|
||||
ifeq ($(CONFIG),clang)
|
||||
-CXX = clang++
|
||||
+CXX = $(HOME)/AFLplusplus/afl-c++
|
||||
CXXFLAGS += -std=$(CXXSTD) $(OPT_LEVEL)
|
||||
ifeq ($(ENABLE_LTO),1)
|
||||
LINKFLAGS += -fuse-ld=lld
|
||||
EOF
|
||||
make -C yosys clean && make -C yosys -j
|
||||
```
|
||||
|
||||
You probably need to configure coredumps to work normally instead of going through some OS service:
|
||||
```
|
||||
echo core | sudo tee /proc/sys/kernel/core_pattern
|
||||
```
|
||||
|
||||
## Running the fuzzer
|
||||
|
||||
Generate some initial testcases using Grammar-Mutator:
|
||||
```
|
||||
(cd $HOME/Grammar-Mutator; rm -rf seeds trees; ./grammar_generator-rtlil 100 1000 ./seeds ./trees)
|
||||
```
|
||||
|
||||
Now run AFL++.
|
||||
```
|
||||
(cd $HOME/Grammar-Mutator; \
|
||||
AFL_CUSTOM_MUTATOR_LIBRARY=./libgrammarmutator-rtlil.so \
|
||||
AFL_CUSTOM_MUTATOR_ONLY=1 \
|
||||
AFL_BENCH_UNTIL_CRASH=1 \
|
||||
YOSYS_WORK_UNITS_PER_THREAD=1 \
|
||||
YOSYS_ABORT_ON_LOG_ERROR=1 \
|
||||
$HOME/AFLplusplus/afl-fuzz -t 5000 -m none -i seeds -o out -- \
|
||||
$HOME/yosys/yosys -p 'read_rtlil -legalize @@; design -save init; old_opt_merge; design -save old; design -load init; opt_merge; design_equal old' \
|
||||
)
|
||||
```
|
||||
This will run the fuzzer until the first crash (including any pass output mismatches) and then stop.
|
||||
Or if you're lucky, the fuzzer will run indefinitely. This uses very little parallelism; if it doesn't find any errors right away, you can increase the test throughput by running AFL++ in parallel using the instructions [here](https://aflplus.plus/docs/parallel_fuzzing).
|
||||
|
||||
## Working with fuzz test failures
|
||||
|
||||
Any failing testcases will be dropped in `$HOME/Grammar-Mutator/out/default/crashes`.
|
||||
Run `yosys -p 'read_rtlil -legalize ... ; dump'` to get the testcase as legalized RTLIL.
|
||||
|
||||
## Notes on generating semantically valid RTLIL
|
||||
|
||||
`Grammar-Mutator` generates RTLIL files according to the context-free grammar in `rtlil-fuzz-grammar.json`.
|
||||
However, the testcases must also be semantically valid, e.g. references to wires should only refer to
|
||||
wires that actually exist. These constraints cannot reasonably be expresed in a CFG. Therefore we
|
||||
have added a `-legalize` option to the `read_rtlil` command. When `-legalize` is set, when `read_rtlil`
|
||||
detects a failed semantic check, instead of erroring out it emits a warning and patches the incoming RTLIL
|
||||
to make it valid.
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
set -e
|
||||
for x in *.ys; do
|
||||
echo "Running $x.."
|
||||
|
|
|
|||
19
tests/proc/bug5572.ys
Normal file
19
tests/proc/bug5572.ys
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
read_rtlil << EOT
|
||||
attribute \top 1
|
||||
module \top
|
||||
wire width 1 \sig
|
||||
wire width 1 \val
|
||||
|
||||
process $2
|
||||
switch \sig [0]
|
||||
case 1'0
|
||||
case 1'1
|
||||
case
|
||||
assign \val [0] 1'1
|
||||
end
|
||||
end
|
||||
end
|
||||
EOT
|
||||
proc_rmdead
|
||||
proc_clean
|
||||
select -assert-none p:*
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
set -e
|
||||
for x in *.ys; do
|
||||
echo "Running $x.."
|
||||
|
|
|
|||
20
tests/pyosys/test_design_run_pass.py
Normal file
20
tests/pyosys/test_design_run_pass.py
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
from pathlib import Path
|
||||
from pyosys import libyosys as ys
|
||||
|
||||
__file_dir__ = Path(__file__).absolute().parent
|
||||
add_sub = __file_dir__.parent / "arch" / "common" / "add_sub.v"
|
||||
|
||||
base = ys.Design()
|
||||
base.run_pass(["read_verilog", str(add_sub)])
|
||||
base.run_pass("hierarchy -top top")
|
||||
base.run_pass(["proc"])
|
||||
base.run_pass("equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5")
|
||||
|
||||
postopt = ys.Design()
|
||||
postopt.run_pass("design -load postopt")
|
||||
postopt.run_pass(["cd", "top"])
|
||||
postopt.run_pass("select -assert-min 25 t:LUT4")
|
||||
postopt.run_pass("select -assert-max 26 t:LUT4")
|
||||
postopt.run_pass(["select", "-assert-count", "10", "t:PFUMX"])
|
||||
postopt.run_pass(["select", "-assert-count", "6", "t:L6MUX21"])
|
||||
postopt.run_pass("select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D")
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
set -e
|
||||
for x in *.ys; do
|
||||
echo "Running $x.."
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
set -e
|
||||
for x in *.ys; do
|
||||
echo "Running $x.."
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
|
||||
# run this test many times:
|
||||
# time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done'
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
|
||||
OPTIND=1
|
||||
seed="" # default to no seed specified
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
|
||||
OPTIND=1
|
||||
seed="" # default to no seed specified
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
#/bin/bash -e
|
||||
source ../common-env.sh
|
||||
|
||||
./runone.sh svinterface1
|
||||
./runone.sh svinterface_at_top
|
||||
|
|
|
|||
28
tests/techmap/abc_speed_gia_only.script
Normal file
28
tests/techmap/abc_speed_gia_only.script
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
&st
|
||||
&dch -r
|
||||
&nf
|
||||
&st
|
||||
&syn2
|
||||
&if -g -K 6
|
||||
&synch2 -r
|
||||
&nf
|
||||
&st
|
||||
&syn2
|
||||
&if -g -K 6
|
||||
&synch2 -r
|
||||
&nf
|
||||
&st
|
||||
&syn2
|
||||
&if -g -K 6
|
||||
&synch2 -r
|
||||
&nf
|
||||
&st
|
||||
&syn2
|
||||
&if -g -K 6
|
||||
&synch2 -r
|
||||
&nf
|
||||
&st
|
||||
&syn2
|
||||
&if -g -K 6
|
||||
&synch2 -r
|
||||
&nf
|
||||
13
tests/techmap/abc_temp_dir_sanitization.ys
Normal file
13
tests/techmap/abc_temp_dir_sanitization.ys
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
read_verilog <<EOT
|
||||
module simple(I1, I2, O);
|
||||
input wire I1;
|
||||
input wire I2;
|
||||
output wire O;
|
||||
|
||||
assign O = I1 | I2;
|
||||
endmodule
|
||||
EOT
|
||||
techmap
|
||||
|
||||
logger -warn " /tmp/" -werror " /tmp/"
|
||||
abc -g all
|
||||
2
tests/techmap/bug5495.abc
Normal file
2
tests/techmap/bug5495.abc
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
|
||||
fraig_store; fraig_restore
|
||||
12
tests/techmap/bug5495.sh
Executable file
12
tests/techmap/bug5495.sh
Executable file
|
|
@ -0,0 +1,12 @@
|
|||
#!/usr/bin/env bash
|
||||
|
||||
if ! which timeout ; then
|
||||
echo "No 'timeout', skipping test"
|
||||
exit 0
|
||||
fi
|
||||
|
||||
if ! timeout 10 ../../yosys bug5495.v -p 'hierarchy; techmap; abc -script bug5495.abc' ; then
|
||||
echo "Yosys failed to complete"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
7
tests/techmap/bug5495.v
Normal file
7
tests/techmap/bug5495.v
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
module simple(I1, I2, O);
|
||||
input wire I1;
|
||||
input wire I2;
|
||||
output wire O;
|
||||
|
||||
assign O = I1 | I2;
|
||||
endmodule
|
||||
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Reference in a new issue