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fix width of post-increment/decrement expressions

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Zachary Snow 2023-09-18 23:35:18 -04:00
parent 7d07615dee
commit 28e99f2b8c
2 changed files with 14 additions and 1 deletions
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13
tests/verilog/asgn_expr.sv
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@ -56,5 +56,18 @@ module top;
check(96, 200, 24);
y = (z >>= 1'sb1) * 2; // shift is implicitly cast to unsigned
check(96, 24, 12);
// check width of post-increment expressions
z = (y = 0);
begin
byte w;
w = 0;
x = {1'b1, ++w};
check(257, 0, 0);
assert (w == 1);
x = {2'b10, w++};
check(513, 0, 0);
assert (w == 2);
end
end
endmodule