From 28e99f2b8c50557e0376fbded1c77236a987ecec Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Mon, 18 Sep 2023 23:35:18 -0400
Subject: [PATCH] fix width of post-increment/decrement expressions
---
frontends/verilog/verilog_parser.y | 2 +-
tests/verilog/asgn_expr.sv | 13 +++++++++++++
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 04bf2c87e..cb8c453c0 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -325,7 +325,7 @@ static AstNode *addIncOrDecExpr(AstNode *lhs, dict<IdString, AstNode*> *attr, AS
log_assert(stmt->type == AST_ASSIGN_EQ);
AstNode *expr = stmt->children[0]->clone();
if (undo) {
- AstNode *minus_one = AstNode::mkconst_int(-1, true);
+ AstNode *minus_one = AstNode::mkconst_int(-1, true, 1);
expr = new AstNode(op, expr, minus_one);
}
SET_AST_NODE_LOC(expr, begin, end);
diff --git a/tests/verilog/asgn_expr.sv b/tests/verilog/asgn_expr.sv
index 9b874ede3..25f9caa33 100644
--- a/tests/verilog/asgn_expr.sv
+++ b/tests/verilog/asgn_expr.sv
@@ -56,5 +56,18 @@ module top;
check(96, 200, 24);
y = (z >>= 1'sb1) * 2; // shift is implicitly cast to unsigned
check(96, 24, 12);
+
+ // check width of post-increment expressions
+ z = (y = 0);
+ begin
+ byte w;
+ w = 0;
+ x = {1'b1, ++w};
+ check(257, 0, 0);
+ assert (w == 1);
+ x = {2'b10, w++};
+ check(513, 0, 0);
+ assert (w == 2);
+ end
end
endmodule