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fix width of post-increment/decrement expressions

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This commit is contained in:
Zachary Snow 2023-09-18 23:35:18 -04:00
parent 7d07615dee
commit 28e99f2b8c
2 changed files with 14 additions and 1 deletions
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2
frontends/verilog/verilog_parser.y
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@ -325,7 +325,7 @@ static AstNode *addIncOrDecExpr(AstNode *lhs, dict<IdString, AstNode*> *attr, AS
log_assert(stmt->type == AST_ASSIGN_EQ);
AstNode *expr = stmt->children[0]->clone();
if (undo) {
AstNode *minus_one = AstNode::mkconst_int(-1, true);
AstNode *minus_one = AstNode::mkconst_int(-1, true, 1);
expr = new AstNode(op, expr, minus_one);
}
SET_AST_NODE_LOC(expr, begin, end);