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Added test cases

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Miodrag Milanovic 2022-02-15 09:35:53 +01:00
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tests/sim/sim_adlatch.ys Normal file
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read_verilog adlatch.v
synth
#TODO: adlatch is not emited
stat
#select -assert-count 1 t:$adlatch
sim -r tb_adlatch.fst -scope tb_adlatch.uut -sim-cmp adlatch