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proc_mux: default to case src when action src is missing

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This commit is contained in:
Emil J. Tywoniak 2025-11-02 12:41:55 +01:00
parent 0c8e008ce7
commit 26e293d71f
1 changed files with 10 additions and 5 deletions
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15
passes/proc/proc_mux.cc
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@ -32,7 +32,8 @@ using SnippetSourceMap = dict<std::pair<int, const RTLIL::CaseRule*>, const Cons
struct SnippetSourceMapBuilder { struct SnippetSourceMapBuilder {
SnippetSourceMap map; SnippetSourceMap map;
void insert(int snippet, const RTLIL::CaseRule* cs, const RTLIL::SyncAction& action) { void insert(int snippet, const RTLIL::CaseRule* cs, const RTLIL::SyncAction& action) {
map[std::make_pair(snippet, cs)] = &action.src; if (action.src.size())
map[std::make_pair(snippet, cs)] = &action.src;
} }
}; };
@ -42,6 +43,11 @@ struct SnippetSourceMapper {
auto src_it = map.find(std::make_pair(snippet, cs)); auto src_it = map.find(std::make_pair(snippet, cs));
if (src_it != map.end()) { if (src_it != map.end()) {
sources.insert(src_it->second->decode_string()); sources.insert(src_it->second->decode_string());
} else {
auto cs_src = cs->get_src_attribute();
if (cs_src.size()) {
sources.insert(cs_src);
}
} }
} }
@ -168,7 +174,7 @@ struct SnippetSwCache
} }
}; };
void apply_attrs(RTLIL::Cell *cell, const RTLIL::SwitchRule *sw, const RTLIL::CaseRule *cs) void apply_attrs(RTLIL::Cell *cell, const RTLIL::CaseRule *cs)
{ {
Const old_src; Const old_src;
if (cell->attributes.count(ID::src)) { if (cell->attributes.count(ID::src)) {
@ -220,7 +226,7 @@ struct MuxGenCtx {
{ {
// create compare cell // create compare cell
RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str(), cmp_wire->width), ifxmode ? ID($eqx) : ID($eq)); RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str(), cmp_wire->width), ifxmode ? ID($eqx) : ID($eq));
apply_attrs(eq_cell, sw, cs); apply_attrs(eq_cell, cs);
eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(0); eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(0);
@ -246,7 +252,7 @@ struct MuxGenCtx {
// reduce cmp vector to one logic signal // reduce cmp vector to one logic signal
RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", ID($reduce_or)); RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", ID($reduce_or));
apply_attrs(any_cell, sw, cs); apply_attrs(any_cell, cs);
any_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); any_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
any_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cmp_wire->width); any_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cmp_wire->width);
@ -280,7 +286,6 @@ struct MuxGenCtx {
// create the multiplexer itself // create the multiplexer itself
RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), ID($mux)); RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), ID($mux));
apply_attrs(mux_cell, sw, cs);
mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size()); mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size());
mux_cell->setPort(ID::A, else_signal); mux_cell->setPort(ID::A, else_signal);