From 26e293d71f00a1174aad493f9c13357efbf275dc Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Sun, 2 Nov 2025 12:41:55 +0100
Subject: [PATCH] proc_mux: default to case src when action src is missing

---
 passes/proc/proc_mux.cc | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index 7d8b2ed57..f0433d6b8 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -32,7 +32,8 @@ using SnippetSourceMap = dict<std::pair<int, const RTLIL::CaseRule*>, const Cons
 struct SnippetSourceMapBuilder {
 	SnippetSourceMap map;
 	void insert(int snippet, const RTLIL::CaseRule* cs, const RTLIL::SyncAction& action) {
-		map[std::make_pair(snippet, cs)] = &action.src;
+		if (action.src.size())
+			map[std::make_pair(snippet, cs)] = &action.src;
 	}
 
 };
@@ -42,6 +43,11 @@ struct SnippetSourceMapper {
 		auto src_it = map.find(std::make_pair(snippet, cs));
 		if (src_it != map.end()) {
 			sources.insert(src_it->second->decode_string());
+		} else {
+			auto cs_src = cs->get_src_attribute();
+			if (cs_src.size()) {
+				sources.insert(cs_src);
+			}
 		}
 	}
 
@@ -168,7 +174,7 @@ struct SnippetSwCache
 	}
 };
 
-void apply_attrs(RTLIL::Cell *cell, const RTLIL::SwitchRule *sw, const RTLIL::CaseRule *cs)
+void apply_attrs(RTLIL::Cell *cell, const RTLIL::CaseRule *cs)
 {
 	Const old_src;
 	if (cell->attributes.count(ID::src)) {
@@ -220,7 +226,7 @@ struct MuxGenCtx {
 			{
 				// create compare cell
 				RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str(), cmp_wire->width), ifxmode ? ID($eqx) : ID($eq));
-				apply_attrs(eq_cell, sw, cs);
+				apply_attrs(eq_cell, cs);
 
 				eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
 				eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(0);
@@ -246,7 +252,7 @@ struct MuxGenCtx {
 
 			// reduce cmp vector to one logic signal
 			RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", ID($reduce_or));
-			apply_attrs(any_cell, sw, cs);
+			apply_attrs(any_cell, cs);
 
 			any_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
 			any_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cmp_wire->width);
@@ -280,7 +286,6 @@ struct MuxGenCtx {
 
 		// create the multiplexer itself
 		RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), ID($mux));
-		apply_attrs(mux_cell, sw, cs);
 
 		mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size());
 		mux_cell->setPort(ID::A, else_signal);