mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-12 20:18:20 +00:00
Code Activity

More undef-propagation related fixes

Browse source
This commit is contained in:
Clifford Wolf 2013-11-08 11:40:36 +01:00
parent 9f49d538e1
commit 259cc1391e
2 changed files with 9 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
frontends/ast/genrtlil.cc
View file

@ -1116,6 +1116,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
detectSignWidth(width_hint, sign_hint); detectSignWidth(width_hint, sign_hint);
RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint); RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint); RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
#if 0
int width = std::max(left.width, right.width); int width = std::max(left.width, right.width);
if (width > width_hint && width_hint > 0) if (width > width_hint && width_hint > 0)
width = width_hint; width = width_hint;
@ -1127,6 +1128,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (type == AST_MUL) if (type == AST_MUL)
width = std::min(left.width + right.width, width_hint); width = std::min(left.width + right.width, width_hint);
} }
#else
int width = std::max(std::max(left.width, right.width), width_hint);
#endif
is_signed = children[0]->is_signed && children[1]->is_signed; is_signed = children[0]->is_signed && children[1]->is_signed;
return binop2rtlil(this, type_name, width, left, right); return binop2rtlil(this, type_name, width, left, right);
} }

5
kernel/calc.cc
View file

@ -69,6 +69,9 @@ static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_
static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_bit_pos) static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_bit_pos)
{ {
if (undef_bit_pos >= 0)
return RTLIL::Const(RTLIL::State::Sx, result_len);
BigUnsigned mag = val.getMagnitude(); BigUnsigned mag = val.getMagnitude();
RTLIL::Const result(0, result_len); RTLIL::Const result(0, result_len);
@ -87,9 +90,11 @@ static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_b
} }
} }
#if 0
if (undef_bit_pos >= 0) if (undef_bit_pos >= 0)
for (int i = undef_bit_pos; i < result_len; i++) for (int i = undef_bit_pos; i < result_len; i++)
result.bits[i] = RTLIL::State::Sx; result.bits[i] = RTLIL::State::Sx;
#endif
return result; return result;
} }