diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 2e8ab7492..25781ae23 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1116,6 +1116,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				detectSignWidth(width_hint, sign_hint);
 			RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
 			RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
+		#if 0
 			int width = std::max(left.width, right.width);
 			if (width > width_hint && width_hint > 0)
 				width = width_hint;
@@ -1127,6 +1128,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				if (type == AST_MUL)
 					width = std::min(left.width + right.width, width_hint);
 			}
+		#else
+			int width = std::max(std::max(left.width, right.width), width_hint);
+		#endif
 			is_signed = children[0]->is_signed && children[1]->is_signed;
 			return binop2rtlil(this, type_name, width, left, right);
 		}
diff --git a/kernel/calc.cc b/kernel/calc.cc
index 68a382cc8..61025104d 100644
--- a/kernel/calc.cc
+++ b/kernel/calc.cc
@@ -69,6 +69,9 @@ static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_
 
 static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_bit_pos)
 {
+	if (undef_bit_pos >= 0)
+		return RTLIL::Const(RTLIL::State::Sx, result_len);
+
 	BigUnsigned mag = val.getMagnitude();
 	RTLIL::Const result(0, result_len);
 
@@ -87,9 +90,11 @@ static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_b
 		}
 	}
 
+#if 0
 	if (undef_bit_pos >= 0)
 		for (int i = undef_bit_pos; i < result_len; i++)
 			result.bits[i] = RTLIL::State::Sx;
+#endif
 
 	return result;
 }