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Smallfixes

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This commit is contained in:
Akash Levy 2025-02-19 10:46:06 -08:00
parent 87e730a01b
commit 241f6370bd
1 changed files with 3 additions and 2 deletions
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5
passes/cmds/splitnets.cc
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@ -204,7 +204,7 @@ struct SplitnetsPass : public Pass {
for (auto &chunk : sig.chunks()) { for (auto &chunk : sig.chunks()) {
if (chunk.wire == NULL) if (chunk.wire == NULL)
continue; continue;
if ((flag_ports_only && (chunk.wire->port_id != 0) || if ((flag_ports_only && (chunk.wire->port_id != 0)) ||
(!flag_ports_only && (chunk.wire->port_id == 0 || flag_ports))) { (!flag_ports_only && (chunk.wire->port_id == 0 || flag_ports))) {
if (chunk.offset != 0) if (chunk.offset != 0)
split_wires_at[chunk.wire].insert(chunk.offset); split_wires_at[chunk.wire].insert(chunk.offset);
@ -226,9 +226,10 @@ struct SplitnetsPass : public Pass {
else else
{ {
for (auto wire : module->wires()) { for (auto wire : module->wires()) {
if (flag_ports_only) if (flag_ports_only) {
if (wire->width > 1 && (wire->port_id != 0) && design->selected(module, wire)) if (wire->width > 1 && (wire->port_id != 0) && design->selected(module, wire))
worker.splitmap[wire] = std::vector<RTLIL::SigBit>(); worker.splitmap[wire] = std::vector<RTLIL::SigBit>();
}
else if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, wire)) else if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, wire))
worker.splitmap[wire] = std::vector<RTLIL::SigBit>(); worker.splitmap[wire] = std::vector<RTLIL::SigBit>();
} }