From 241f6370bda07d723d0217bde414aea2b8ea4ff3 Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Wed, 19 Feb 2025 10:46:06 -0800
Subject: [PATCH] Smallfixes

---
 passes/cmds/splitnets.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index 388f125d8..c900bb472 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -204,7 +204,7 @@ struct SplitnetsPass : public Pass {
 					for (auto &chunk : sig.chunks()) {
 						if (chunk.wire == NULL)
 							continue;
-						if ((flag_ports_only && (chunk.wire->port_id != 0) ||
+						if ((flag_ports_only && (chunk.wire->port_id != 0)) ||
 						   (!flag_ports_only && (chunk.wire->port_id == 0 || flag_ports))) {
 							if (chunk.offset != 0)
 								split_wires_at[chunk.wire].insert(chunk.offset);
@@ -226,9 +226,10 @@ struct SplitnetsPass : public Pass {
 			else
 			{
 				for (auto wire : module->wires()) {
-					if (flag_ports_only)
+					if (flag_ports_only) {
 						if (wire->width > 1 && (wire->port_id != 0) && design->selected(module, wire))
 							worker.splitmap[wire] = std::vector<RTLIL::SigBit>();
+					}
 					else if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, wire))
 						worker.splitmap[wire] = std::vector<RTLIL::SigBit>();
 				}