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rtlil: replace SigSig actions with new type SyncAction
(cherry picked from commit 94a53e08bc)
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parent
0372902ad0
commit
2330860c48
19 changed files with 297 additions and 238 deletions
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@ -122,6 +122,7 @@ namespace RTLIL
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struct CaseRule;
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struct SwitchRule;
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struct MemWriteAction;
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struct SyncAction;
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struct SyncRule;
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struct Process;
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struct Binding;
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@ -1340,6 +1341,10 @@ struct RTLIL::AttrObject
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// void set_strpool_attribute(IdString id, const pool<string> &data);
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// void add_strpool_attribute(IdString id, const pool<string> &data);
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// pool<string> get_strpool_attribute(RTLIL::IdString id) const;
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void transfer_attribute(const AttrObject* from, const IdString& attr) {
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if (from->has_attribute(attr))
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attributes[attr] = from->attributes.at(attr);
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}
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void set_hdlname_attribute(const vector<string> &hierarchy);
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vector<string> get_hdlname_attribute() const;
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@ -2359,6 +2364,7 @@ public:
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// Transfer src from `source` verbatim (same pool). Asserts attached
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// to a design.
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void adopt_src_from(const RTLIL::AttrObject *source);
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void transfer_src_attribute(const RTLIL::AttrObject *source) { adopt_src_from(source); }
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void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
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bool known_driver() const { return driverCell_ != nullptr; }
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@ -2465,6 +2471,7 @@ public:
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void set_src_attribute(TwineRef src);
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std::string get_src_attribute() const;
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void adopt_src_from(const RTLIL::AttrObject *source);
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void transfer_src_attribute(const RTLIL::AttrObject *source) { adopt_src_from(source); }
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void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
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// access cell ports
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@ -2517,7 +2524,7 @@ struct RTLIL::CaseRule : public RTLIL::AttrObject
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RTLIL::Module *module = nullptr;
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std::vector<RTLIL::SigSpec> compare;
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std::vector<RTLIL::SigSig> actions;
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std::vector<RTLIL::SyncAction> actions;
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std::vector<RTLIL::SwitchRule*> switches;
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~CaseRule();
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@ -2592,11 +2599,17 @@ struct RTLIL::MemWriteAction : RTLIL::AttrObject
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void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
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};
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struct RTLIL::SyncAction
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{
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RTLIL::SigSpec lhs;
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RTLIL::SigSpec rhs;
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};
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struct RTLIL::SyncRule
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{
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RTLIL::SyncType type;
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RTLIL::SigSpec signal;
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std::vector<RTLIL::SigSig> actions;
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std::vector<RTLIL::SyncAction> actions;
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std::vector<RTLIL::MemWriteAction> mem_write_actions;
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template<typename T> void rewrite_sigspecs(T &functor);
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@ -3260,8 +3273,8 @@ void RTLIL::CaseRule::rewrite_sigspecs(T &functor) {
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for (auto &it : compare)
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functor(it);
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for (auto &it : actions) {
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functor(it.first);
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functor(it.second);
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functor(it.lhs);
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functor(it.rhs);
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}
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for (auto it : switches)
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it->rewrite_sigspecs(functor);
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@ -3272,7 +3285,7 @@ void RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {
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for (auto &it : compare)
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functor(it);
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for (auto &it : actions) {
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functor(it.first, it.second);
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functor(it.lhs, it.rhs);
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}
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for (auto it : switches)
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it->rewrite_sigspecs2(functor);
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@ -3299,8 +3312,8 @@ void RTLIL::SyncRule::rewrite_sigspecs(T &functor)
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{
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functor(signal);
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for (auto &it : actions) {
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functor(it.first);
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functor(it.second);
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functor(it.lhs);
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functor(it.rhs);
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}
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for (auto &it : mem_write_actions) {
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functor(it.address);
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@ -3314,7 +3327,7 @@ void RTLIL::SyncRule::rewrite_sigspecs2(T &functor)
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{
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functor(signal);
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for (auto &it : actions) {
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functor(it.first, it.second);
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functor(it.lhs, it.rhs);
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}
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for (auto &it : mem_write_actions) {
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functor(it.address);
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