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Merge d786262ad6 into 262b00d5e5

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Kelvin Chung 2025-07-31 09:54:10 +01:00 • committed by GitHub
commit 22e50bee4d
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3 changed files with 85 additions and 19 deletions
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9
passes/memory/memory.cc
View file

@ -31,7 +31,7 @@ struct MemoryPass : public Pass {
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" memory [-norom] [-nomap] [-nordff] [-nowiden] [-nosat] [-memx] [-no-rw-check] [-bram <bram_rules>] [selection]\n");
log(" memory [-external-init] [-norom] [-nomap] [-nordff] [-nowiden] [-nosat] [-memx] [-no-rw-check] [-bram <bram_rules>] [selection]\n");
log("\n");
log("This pass calls all the other memory_* passes in a useful order:\n");
log("\n");
@ -59,6 +59,7 @@ struct MemoryPass : public Pass {
bool flag_nomap = false;
bool flag_nordff = false;
bool flag_memx = false;
string opt_mem_opts;
string memory_dff_opts;
string memory_bram_opts;
string memory_share_opts;
@ -68,6 +69,10 @@ struct MemoryPass : public Pass {
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-external-init") {
opt_mem_opts += " -external-init";
continue;
}
if (args[argidx] == "-norom") {
flag_norom = true;
continue;
@ -105,7 +110,7 @@ struct MemoryPass : public Pass {
}
extra_args(args, argidx, design);
Pass::call(design, "opt_mem");
Pass::call(design, "opt_mem" + opt_mem_opts);
Pass::call(design, "opt_mem_priority");
Pass::call(design, "opt_mem_feedback");
if (!flag_norom)

22
passes/opt/opt_mem.cc
View file

@ -17,10 +17,10 @@
*
*/
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#include "kernel/mem.h"
#include "kernel/ff.h"
#include "kernel/mem.h"
#include "kernel/sigtools.h"
#include "kernel/yosys.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -35,17 +35,23 @@ struct OptMemPass : public Pass {
log("\n");
log("This pass performs various optimizations on memories in the design.\n");
log("\n");
log(" -external-init\n");
log(" Assume memories are initialised externally, i.e. the memory\n");
log(" is pre-populated so content is available even when there is no\n");
log(" write within the circuit.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing OPT_MEM pass (optimize memories).\n");
bool external_init = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
// if (args[argidx] == "-nomux") {
// mode_nomux = true;
// continue;
// }
if (args[argidx] == "-external-init") {
external_init = true;
continue;
}
break;
}
extra_args(args, argidx, design);
@ -102,7 +108,7 @@ struct OptMemPass : public Pass {
}
std::vector<int> swizzle;
for (int i = 0; i < mem.width; i++) {
if (!always_0[i] && !always_1[i]) {
if ((!always_0[i] && !always_1[i]) || external_init) {
swizzle.push_back(i);
continue;
}

55
tests/opt/opt_mem_external.ys Normal file
View file

@ -0,0 +1,55 @@
read_verilog << EOF
module Mem #(
parameter WIDTH = 8,
parameter SIZE = 16,
parameter IDX_SIZE = 16
) (
input wire [WIDTH-1:0] addr,
input wire [WIDTH-1:0] write_data,
input wire write_en,
input wire clk,
output reg [WIDTH-1:0] read_data,
);
reg [WIDTH-1:0] mem[SIZE-1:0];
always @(posedge clk) begin
if (write_en)
mem[addr0[IDX_SIZE-1:0]] <= write_data;
read_data <= mem[addr0[IDX_SIZE-1:0]];
end
endmodule
module test_keep_at_instance (clk, addr, data);
input wire clk;
input wire [15:0] addr;
output wire[7:0] data;
Mem mem (
.clk(clk),
.addr(addr),
.read_data(data),
.write_en(1'b0),
.write_data()
);
endmodule
EOF
hierarchy -auto-top;
flatten;
proc;
select -assert-any t:$mem*
opt_mem -external-init
select -assert-any t:$mem*
select -assert-any t:$mem*
opt_mem
select -assert-none t:$mem*