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55 lines
881 B
Text
55 lines
881 B
Text
read_verilog << EOF
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module Mem #(
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parameter WIDTH = 8,
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parameter SIZE = 16,
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parameter IDX_SIZE = 16
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) (
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input wire [WIDTH-1:0] addr,
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input wire [WIDTH-1:0] write_data,
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input wire write_en,
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input wire clk,
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output reg [WIDTH-1:0] read_data,
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);
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reg [WIDTH-1:0] mem[SIZE-1:0];
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always @(posedge clk) begin
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if (write_en)
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mem[addr0[IDX_SIZE-1:0]] <= write_data;
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read_data <= mem[addr0[IDX_SIZE-1:0]];
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end
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endmodule
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module test_keep_at_instance (clk, addr, data);
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input wire clk;
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input wire [15:0] addr;
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output wire[7:0] data;
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Mem mem (
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.clk(clk),
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.addr(addr),
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.read_data(data),
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.write_en(1'b0),
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.write_data()
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);
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endmodule
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EOF
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hierarchy -auto-top;
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flatten;
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proc;
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select -assert-any t:$mem*
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opt_mem -external-init
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select -assert-any t:$mem*
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select -assert-any t:$mem*
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opt_mem
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select -assert-none t:$mem*
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