Merge pull request #4705 from YosysHQ/docs-preview-lintonly

Emphasise that read_verilog doesn't lint

README.md

@@ -266,6 +266,16 @@ The command ``prep`` provides a good default word-level synthesis script, as
 used in SMT-based formal verification.
 
 
+Additional information
+======================
+
+The ``read_verilog`` command, used by default when calling ``read`` with Verilog
+source input, does not perform syntax checking.  You should instead lint your
+source with another tool such as
+[Verilator](https://www.veripool.org/verilator/) first, e.g. by calling
+``verilator --lint-only``.
+
+
 Unsupported Verilog-2005 Features
 =================================