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	Docs: Less exaggeration
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			@ -264,8 +264,8 @@ Additional information
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======================
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The ``read_verilog`` command, used by default when calling ``read`` with Verilog
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source input, does not perform any syntax checking.  You should instead lint
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your source with another tool such as
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source input, does not perform syntax checking.  You should instead lint your
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source with another tool such as
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[Verilator](https://www.veripool.org/verilator/) first, e.g. by calling
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``verilator --lint-only``.
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