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test dlatchsr and adlatch

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This commit is contained in:
Miodrag Milanovic 2022-02-16 13:58:51 +01:00
parent 271ac28b41
commit 21baf48e04
4 changed files with 94 additions and 4 deletions
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12
tests/sim/sim_adlatch.ys
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@ -1,6 +1,10 @@
read_verilog adlatch.v
synth
#TODO: adlatch is not emited
read_verilog -icells <<EOT
module adlatch(input d, rst, en, output reg q);
$adlatch #(.EN_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(1'b0), .WIDTH(1)) uut (.EN(en), .ARST(rst), .D(d), .Q(q));
endmodule
EOT
proc
opt_dff
stat
#select -assert-count 1 t:$adlatch
select -assert-count 1 t:$adlatch
sim -r tb_adlatch.fst -scope tb_adlatch.uut -sim-cmp adlatch