diff --git a/tests/sim/dlatchsr.v b/tests/sim/dlatchsr.v
new file mode 100644
index 000000000..1d13ac2ad
--- /dev/null
+++ b/tests/sim/dlatchsr.v
@@ -0,0 +1,11 @@
+module dlatchsr( input d, set, clr, en, output reg q );
+	always @* begin
+		if ( clr )
+			q = 0;
+		else if (set)
+			q = 1;
+		else
+			if (en)
+				q = d;
+	end
+endmodule
diff --git a/tests/sim/sim_adlatch.ys b/tests/sim/sim_adlatch.ys
index 787b00c39..eece7dc0d 100644
--- a/tests/sim/sim_adlatch.ys
+++ b/tests/sim/sim_adlatch.ys
@@ -1,6 +1,10 @@
-read_verilog adlatch.v
-synth
-#TODO: adlatch is not emited
+read_verilog -icells <<EOT
+module adlatch(input d, rst, en, output reg q);
+$adlatch #(.EN_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(1'b0), .WIDTH(1)) uut (.EN(en), .ARST(rst), .D(d), .Q(q));
+endmodule
+EOT
+proc
+opt_dff
 stat
-#select -assert-count 1 t:$adlatch
+select -assert-count 1 t:$adlatch
 sim -r tb_adlatch.fst -scope tb_adlatch.uut -sim-cmp adlatch
diff --git a/tests/sim/sim_dlatchsr.ys b/tests/sim/sim_dlatchsr.ys
new file mode 100644
index 000000000..c83051c8b
--- /dev/null
+++ b/tests/sim/sim_dlatchsr.ys
@@ -0,0 +1,10 @@
+read_verilog -icells <<EOT
+module dlatchsr(input d, set, clr, en, output reg q);
+$dlatchsr #(.EN_POLARITY(1'b1), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b1), .WIDTH(1)) uut (.EN(en), .SET(set), .CLR(clr), .D(d), .Q(q));
+endmodule
+EOT
+proc
+opt_dff
+stat
+select -assert-count 1 t:$dlatchsr
+sim -r tb_dlatchsr.fst -scope tb_dlatchsr.uut -sim-cmp dlatchsr
diff --git a/tests/sim/tb/tb_dlatchsr.v b/tests/sim/tb/tb_dlatchsr.v
new file mode 100755
index 000000000..0105d3288
--- /dev/null
+++ b/tests/sim/tb/tb_dlatchsr.v
@@ -0,0 +1,65 @@
+`timescale 1ns/1ns 
+module tb_dlatchsr();
+	reg d = 0;
+	reg set = 0;
+	reg clr = 0;
+	wire q;
+
+	dlatchsr uut(.d(d),.set(set),.clr(clr),.q(q));
+
+	initial
+	begin
+		$dumpfile("tb_dlatchsr");
+		$dumpvars(0,tb_dlatchsr);
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		clr = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		clr = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		set = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		set = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		$finish;
+	end
+endmodule