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test dlatchsr and adlatch

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Miodrag Milanovic 2022-02-16 13:58:51 +01:00
parent 271ac28b41
commit 21baf48e04
4 changed files with 94 additions and 4 deletions
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tests/sim/dlatchsr.v Normal file
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module dlatchsr( input d, set, clr, en, output reg q );
always @* begin
if ( clr )
q = 0;
else if (set)
q = 1;
else
if (en)
q = d;
end
endmodule