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test dlatchsr and adlatch

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This commit is contained in:
Miodrag Milanovic 2022-02-16 13:58:51 +01:00
parent 271ac28b41
commit 21baf48e04
4 changed files with 94 additions and 4 deletions
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11
tests/sim/dlatchsr.v Normal file
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module dlatchsr( input d, set, clr, en, output reg q );
always @* begin
if ( clr )
q = 0;
else if (set)
q = 1;
else
if (en)
q = d;
end
endmodule

12
tests/sim/sim_adlatch.ys
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@ -1,6 +1,10 @@
read_verilog adlatch.v
synth
#TODO: adlatch is not emited
read_verilog -icells <<EOT
module adlatch(input d, rst, en, output reg q);
$adlatch #(.EN_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(1'b0), .WIDTH(1)) uut (.EN(en), .ARST(rst), .D(d), .Q(q));
endmodule
EOT
proc
opt_dff
stat
#select -assert-count 1 t:$adlatch
select -assert-count 1 t:$adlatch
sim -r tb_adlatch.fst -scope tb_adlatch.uut -sim-cmp adlatch

10
tests/sim/sim_dlatchsr.ys Normal file
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read_verilog -icells <<EOT
module dlatchsr(input d, set, clr, en, output reg q);
$dlatchsr #(.EN_POLARITY(1'b1), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b1), .WIDTH(1)) uut (.EN(en), .SET(set), .CLR(clr), .D(d), .Q(q));
endmodule
EOT
proc
opt_dff
stat
select -assert-count 1 t:$dlatchsr
sim -r tb_dlatchsr.fst -scope tb_dlatchsr.uut -sim-cmp dlatchsr

65
tests/sim/tb/tb_dlatchsr.v Executable file
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`timescale 1ns/1ns
module tb_dlatchsr();
reg d = 0;
reg set = 0;
reg clr = 0;
wire q;
dlatchsr uut(.d(d),.set(set),.clr(clr),.q(q));
initial
begin
$dumpfile("tb_dlatchsr");
$dumpvars(0,tb_dlatchsr);
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
clr = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
clr = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
set = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
set = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
$finish;
end
endmodule