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Merge pull request #2164 from madebr/msvc

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Get yosys building on Visual Studio
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Miodrag Milanović 2020-06-18 12:44:21 +02:00 committed by GitHub
parent c4f20f744b 60fb9cabcf
commit 2123019ac6
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4 changed files with 11 additions and 11 deletions
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2
frontends/verilog/preproc.cc
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@ -591,7 +591,7 @@ read_define_args()
default:
// The only FSM states are 0-2 and we dealt with 2 at the start of the loop.
__builtin_unreachable();
log_assert(false);
}
}

2
frontends/verilog/verilog_parser.y
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@ -1481,7 +1481,7 @@ enum_name_decl:
delete $1;
SET_AST_NODE_LOC(node, @1, @1);
delete node->children[0];
node->children[0] = $2 ?: new AstNode(AST_NONE);
node->children[0] = $2 ? $2 : new AstNode(AST_NONE);
astbuf2->children.push_back(node);
}
;

8
kernel/yosys.h
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@ -117,11 +117,11 @@ extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *p
# define PATH_MAX MAX_PATH
# define isatty _isatty
# define fileno _fileno
# else
// mingw includes `wingdi.h` which defines a TRANSPARENT macro
// that conflicts with X(TRANSPARENT) entry in kernel/constids.inc
# undef TRANSPARENT
# endif
// mingw and msvc include `wingdi.h` which defines a TRANSPARENT macro
// that conflicts with X(TRANSPARENT) entry in kernel/constids.inc
# undef TRANSPARENT
#endif
#ifndef PATH_MAX

10
passes/techmap/extract_counter.cc
View file

@ -795,11 +795,11 @@ struct ExtractCounterPass : public Pass {
pool<RTLIL::IdString> _parallel_cells;
CounterExtractionSettings settings
{
.parallel_cells = _parallel_cells,
.maxwidth = 64,
.minwidth = 2,
.allow_arst = true,
.allowed_dirs = 0,
_parallel_cells, // parallel_cells
64, // maxwidth
2, // minwidth
true, // allow_arst
0, // allowed_dirs
};
size_t argidx;