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This commit is contained in:
Emil J. Tywoniak 2026-06-09 18:50:00 +02:00
parent d13dfc21f4
commit 2117af318c
23 changed files with 1684 additions and 1666 deletions
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2
kernel/celltypes.h
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@ -68,7 +68,7 @@ struct CellTypes
void setup_module(RTLIL::Module *module)
{
pool<RTLIL::IdString> inputs, outputs;
for (RTLIL::IdString wire_name : module->ports) {
for (auto wire_name : module->ports) {
RTLIL::Wire *wire = module->wire(wire_name);
if (wire->port_input)
inputs.insert(wire->name);