diff --git a/.gitmodules b/.gitmodules
index 9f18be11e..d59194376 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -5,3 +5,6 @@
 [submodule "cxxopts"]
 	path = libs/cxxopts
 	url = https://github.com/jarro2783/cxxopts
+[submodule "libs/plf_colony"]
+	path = libs/plf_colony
+	url = git@github.com:mattreecebentley/plf_colony.git
diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc
index d44c9a380..be19646ee 100644
--- a/backends/rtlil/rtlil_backend.cc
+++ b/backends/rtlil/rtlil_backend.cc
@@ -38,7 +38,7 @@ void RTLIL_BACKEND::dump_attributes(std::ostream &f, std::string indent, const R
 	// — the dict no longer holds ID::src under any circumstance. Backends
 	// that want to materialize the pipe-joined literal pass resolve_src.
 	if (design && design->obj_src_id(obj) != Twine::Null) {
-		Twine::Id id = design->obj_src_id(obj);
+		TwineRef id = design->obj_src_id(obj);
 		f << stringf("%s" "attribute \\src ", indent);
 		if (resolve_src) {
 			dump_const(f, RTLIL::Const(design->twines.flatten(id)));
@@ -59,7 +59,7 @@ void RTLIL_BACKEND::dump_twines(std::ostream &f, const RTLIL::Design *design)
 	if (!design || design->twines.size() == 0)
 		return;
 	f << stringf("twines\n");
-	design->twines.for_each_live([&](Twine::Id id, const Twine &n) {
+	design->twines.for_each_live([&](TwineRef id, const Twine &n) {
 		if (n.is_leaf()) {
 			f << stringf("  leaf %u ", id);
 			dump_const(f, RTLIL::Const(n.leaf()));
@@ -70,7 +70,7 @@ void RTLIL_BACKEND::dump_twines(std::ostream &f, const RTLIL::Design *design)
 			f << stringf("\n");
 		} else {
 			f << stringf("  concat %u", id);
-			for (Twine::Id c : n.children())
+			for (TwineRef c : n.children())
 				f << stringf(" %u", c);
 			f << stringf("\n");
 		}
diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc
index a62c52169..6f1db9936 100644
--- a/frontends/aiger2/xaiger.cc
+++ b/frontends/aiger2/xaiger.cc
@@ -122,6 +122,7 @@ struct Xaiger2Frontend : public Frontend {
 		bits[1] = RTLIL::S1;
 
 		std::string type;
+		TwineSearch search(&design->twines);
 		while (map_file >> type) {
 			if (type == "pi") {
 				int pi_idx;
@@ -132,7 +133,7 @@ struct Xaiger2Frontend : public Frontend {
 				int lit = (2 * pi_idx) + 2;
 				if (lit < 0 || lit >= (int) bits.size())
 					log_error("Bad map file: primary input literal out of range\n");
-				Wire *w = module->wire(name);
+				Wire *w = module->wire(search.find(name));
 				if (!w || woffset < 0 || woffset >= w->width)
 					log_error("Map file references non-existent signal bit %s[%d]\n",
 							  name.c_str(), woffset);
@@ -145,7 +146,7 @@ struct Xaiger2Frontend : public Frontend {
 				if (box_seq < 0)
 					log_error("Bad map file: box out of range\n");
 
-				Cell *box = module->cell(RTLIL::escape_id(name));
+				Cell *box = module->cell(search.find(RTLIL::escape_id(name)));
 				if (!box)
 					log_error("Map file references non-existent box %s\n",
 							  name.c_str());
@@ -214,7 +215,7 @@ struct Xaiger2Frontend : public Frontend {
 					for (auto port_id : def->ports) {
 						Wire *port = def->wire(port_id);
 						if (port->port_output) {
-							if (!cell->hasPort(port_id) || cell->getPort(port_id).size() != port->width)
+							if (!cell->hasPort(search.find(port_id)) || cell->getPort(port_id).size() != port->width)
 								log_error("Malformed design (1)\n");
 
 							SigSpec &conn = cell->connections_[port_id];
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 9663405e6..e3f431062 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1123,11 +1123,11 @@ void AST::set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast)
 	// thousands of objects in one file this collapses N copies of a long
 	// path into 1 Leaf + N short Suffix tails.
 	TwinePool *pool = &current_module->design->twines;
-	Twine::Id file_id = pool->intern(*loc.begin.filename);
+	TwineRef file_id = pool->intern(*loc.begin.filename);
 	std::string tail = stringf(":%d.%d-%d.%d",
 			loc.begin.line, loc.begin.column,
 			loc.end.line, loc.end.column);
-	Twine::Id suffix_id = pool->intern_suffix(file_id, tail);
+	TwineRef suffix_id = pool->intern_suffix(file_id, tail);
 	pool->release(file_id); // suffix internally holds a ref now
 	current_module->design->obj_set_src_id(obj, suffix_id);
 	pool->release(suffix_id); // obj_set_src_id retained on obj's behalf
diff --git a/frontends/rtlil/rtlil_frontend.cc b/frontends/rtlil/rtlil_frontend.cc
index f963c655a..faf5a20bb 100644
--- a/frontends/rtlil/rtlil_frontend.cc
+++ b/frontends/rtlil/rtlil_frontend.cc
@@ -58,8 +58,8 @@ struct RTLILFrontendWorker {
 	// parse_twines; consumed by parse_attribute. Parser-side ids retained
 	// during parse_twines are tracked here so they can be released at
 	// end-of-parse — only the cell/wire references should survive.
-	dict<size_t, Twine::Id> twine_remap;
-	std::vector<Twine::Id> twine_parser_holds;
+	dict<size_t, TwineRef> twine_remap;
+	std::vector<TwineRef> twine_parser_holds;
 
 	template <typename... Args>
 	[[noreturn]]
@@ -423,7 +423,7 @@ struct RTLILFrontendWorker {
 
 	void parse_module()
 	{
-		Twine::Id module_name = design->twines.lookup(parse_id());
+		TwineRef module_name = design->twines.lookup(parse_id());
 		expect_eol();
 
 		bool delete_current_module = false;
@@ -587,7 +587,7 @@ struct RTLILFrontendWorker {
 	// referred to a file_id has already adopted the corresponding local_id.
 	void release_twine_parser_holds()
 	{
-		for (Twine::Id id : twine_parser_holds)
+		for (TwineRef id : twine_parser_holds)
 			design->twines.release(id);
 		twine_parser_holds.clear();
 		twine_remap.clear();
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index d67bb29e1..32cfb727a 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -68,7 +68,7 @@ struct CellTypes
 	void setup_module(RTLIL::Module *module)
 	{
 		pool<RTLIL::IdString> inputs, outputs;
-		for (RTLIL::IdString wire_name : module->ports) {
+		for (auto wire_name : module->ports) {
 			RTLIL::Wire *wire = module->wire(wire_name);
 			if (wire->port_input)
 				inputs.insert(wire->name);
diff --git a/kernel/ff.cc b/kernel/ff.cc
index 146b5253e..8581199aa 100644
--- a/kernel/ff.cc
+++ b/kernel/ff.cc
@@ -774,7 +774,7 @@ Cell *FfData::emit() {
 			// Cross-pool (unusual — FfData migrated between
 			// designs). Rebuild the twine structure into the
 			// destination pool, then adopt that fresh id.
-			Twine::Id migrated = dst_pool->copy_from(*src_twine.pool(), src_twine.id());
+			TwineRef migrated = dst_pool->copy_from(*src_twine.pool(), src_twine.id());
 			cell->set_src_id(migrated);
 			dst_pool->release(migrated);
 		}
diff --git a/kernel/ff.h b/kernel/ff.h
index 3e7c24534..04534f244 100644
--- a/kernel/ff.h
+++ b/kernel/ff.h
@@ -173,7 +173,7 @@ struct FfData : FfTypeData {
 	// Stashed src across construction → emit. Refcount-managed so the
 	// source cell's pool slot survives if the cell itself is removed
 	// before emit() runs. Empty when the source cell had no src.
-	Twine::Id src_twine;
+	TwineRef src_twine;
 
 	FfData(Module *module = nullptr, FfInitVals *initvals = nullptr, IdString name = IdString()) : module(module), initvals(initvals), cell(nullptr), name(name) {
 		width = 0;
diff --git a/kernel/mem.cc b/kernel/mem.cc
index 499f5d36c..740b48809 100644
--- a/kernel/mem.cc
+++ b/kernel/mem.cc
@@ -895,9 +895,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
 	// "@N" parse_ref path), and there's no flatten → re-intern → pipe-
 	// leaf round-trip on cells whose src is a Concat node.
 	log_assert(module && module->design);
-	Twine::Id mem_src_id = module->design->obj_src_id(this);
-	std::string mem_src = (mem_src_id != Twine::Null) ?
-			module->design->twines.format_ref(mem_src_id) : std::string();
+	TwineRef mem_src = module->design->obj_src_id(this);
 
 	Cell *c;
 
@@ -1005,7 +1003,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
 		FfData ff(module, initvals, name);
 		// Carry mem's src into the ff via the OwnedTwine handle — same
 		// pool, direct id retain. emit() transfers verbatim.
-		ff.src_twine = mem_src_id;
+		ff.src_twine = mem_src;
 		ff.width = GetSize(port.data);
 		ff.has_clk = true;
 		ff.sig_clk = port.clk;
diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h
index a300948ee..fef0dc32d 100644
--- a/kernel/newcelltypes.h
+++ b/kernel/newcelltypes.h
@@ -19,17 +19,17 @@ constexpr int MAX_CELLS = 300;
 constexpr int MAX_PORTS = 20;
 struct CellTableBuilder {
 	struct PortList {
-		std::array<RTLIL::IdString, MAX_PORTS> ports{};
+		std::array<TwineRef, MAX_PORTS> ports{};
 		size_t count = 0;
 		constexpr PortList() = default;
-		constexpr PortList(std::initializer_list<RTLIL::IdString> init) {
+		constexpr PortList(std::initializer_list<TwineRef> init) {
 			for (auto p : init) {
 				ports[count++] = p;
 			}
 		}
 		constexpr auto begin() const { return ports.begin(); }
 		constexpr auto end() const { return ports.begin() + count; }
-		constexpr bool contains(RTLIL::IdString port) const {
+		constexpr bool contains(TwineRef port) const {
 			for (size_t i = 0; i < count; i++) {
 				if (port == ports[i])
 					return true;
@@ -57,42 +57,42 @@ struct CellTableBuilder {
 	std::array<CellInfo, MAX_CELLS> cells{};
 	size_t count = 0;
 
-	constexpr void setup_type(RTLIL::IdString type, std::initializer_list<RTLIL::IdString> inputs, std::initializer_list<RTLIL::IdString> outputs, const Features& features) {
+	constexpr void setup_type(RTLIL::IdString type, std::initializer_list<TwineRef> inputs, std::initializer_list<TwineRef> outputs, const Features& features) {
 		cells[count++] = {type, PortList(inputs), PortList(outputs), features};
 	}
 	constexpr void setup_internals_other()
 	{
 		Features features {};
 		features.is_tristate = true;
-		setup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, features);
+		setup_type(ID($tribuf), {TW::A, TW::EN}, {TW::Y}, features);
 
 		features = {};
-		setup_type(ID($assert), {ID::A, ID::EN}, {}, features);
-		setup_type(ID($assume), {ID::A, ID::EN}, {}, features);
-		setup_type(ID($live), {ID::A, ID::EN}, {}, features);
-		setup_type(ID($fair), {ID::A, ID::EN}, {}, features);
-		setup_type(ID($cover), {ID::A, ID::EN}, {}, features);
-		setup_type(ID($initstate), {}, {ID::Y}, features);
-		setup_type(ID($anyconst), {}, {ID::Y}, features);
-		setup_type(ID($anyseq), {}, {ID::Y}, features);
-		setup_type(ID($allconst), {}, {ID::Y}, features);
-		setup_type(ID($allseq), {}, {ID::Y}, features);
-		setup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, features);
-		setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, {}, features);
-		setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, {}, features);
-		setup_type(ID($specrule), {ID::SRC_EN, ID::DST_EN, ID::SRC, ID::DST}, {}, features);
-		setup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, {}, features);
-		setup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, {}, features);
-		setup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y}, features);
-		setup_type(ID($get_tag), {ID::A}, {ID::Y}, features);
-		setup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, {}, features);
-		setup_type(ID($original_tag), {ID::A}, {ID::Y}, features);
-		setup_type(ID($future_ff), {ID::A}, {ID::Y}, features);
+		setup_type(ID($assert), {TW::A, TW::EN}, {}, features);
+		setup_type(ID($assume), {TW::A, TW::EN}, {}, features);
+		setup_type(ID($live), {TW::A, TW::EN}, {}, features);
+		setup_type(ID($fair), {TW::A, TW::EN}, {}, features);
+		setup_type(ID($cover), {TW::A, TW::EN}, {}, features);
+		setup_type(ID($initstate), {}, {TW::Y}, features);
+		setup_type(ID($anyconst), {}, {TW::Y}, features);
+		setup_type(ID($anyseq), {}, {TW::Y}, features);
+		setup_type(ID($allconst), {}, {TW::Y}, features);
+		setup_type(ID($allseq), {}, {TW::Y}, features);
+		setup_type(ID($equiv), {TW::A, TW::B}, {TW::Y}, features);
+		setup_type(ID($specify2), {TW::EN, TW::SRC, TW::DST}, {}, features);
+		setup_type(ID($specify3), {TW::EN, TW::SRC, TW::DST, TW::DAT}, {}, features);
+		setup_type(ID($specrule), {TW::SRC_EN, TW::DST_EN, TW::SRC, TW::DST}, {}, features);
+		setup_type(ID($print), {TW::EN, TW::ARGS, TW::TRG}, {}, features);
+		setup_type(ID($check), {TW::A, TW::EN, TW::ARGS, TW::TRG}, {}, features);
+		setup_type(ID($set_tag), {TW::A, TW::SET, TW::CLR}, {TW::Y}, features);
+		setup_type(ID($get_tag), {TW::A}, {TW::Y}, features);
+		setup_type(ID($overwrite_tag), {TW::A, TW::SET, TW::CLR}, {}, features);
+		setup_type(ID($original_tag), {TW::A}, {TW::Y}, features);
+		setup_type(ID($future_ff), {TW::A}, {TW::Y}, features);
 		setup_type(ID($scopeinfo), {}, {}, features);
-		setup_type(ID($input_port), {}, {ID::Y}, features);
-		setup_type(ID($output_port), {ID::A}, {}, features);
-		setup_type(ID($public), {ID::A}, {}, features);
-		setup_type(ID($connect), {ID::A, ID::B}, {}, features);
+		setup_type(ID($input_port), {}, {TW::Y}, features);
+		setup_type(ID($output_port), {TW::A}, {}, features);
+		setup_type(ID($public), {TW::A}, {}, features);
+		setup_type(ID($connect), {TW::A, TW::B}, {}, features);
 	}
 	constexpr void setup_internals_eval()
 	{
@@ -114,48 +114,48 @@ struct CellTableBuilder {
 		};
 
 		for (auto type : unary_ops)
-			setup_type(type, {ID::A}, {ID::Y}, features);
+			setup_type(type, {TW::A}, {TW::Y}, features);
 
 		for (auto type : binary_ops)
-			setup_type(type, {ID::A, ID::B}, {ID::Y}, features);
+			setup_type(type, {TW::A, TW::B}, {TW::Y}, features);
 
 		for (auto type : {ID($mux), ID($pmux), ID($bwmux)})
-			setup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, features);
+			setup_type(type, {TW::A, TW::B, TW::S}, {TW::Y}, features);
 
 		for (auto type : {ID($bmux), ID($demux)})
-			setup_type(type, {ID::A, ID::S}, {ID::Y}, features);
+			setup_type(type, {TW::A, TW::S}, {TW::Y}, features);
 
-		setup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, features);
-		setup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, features);
-		setup_type(ID($macc_v2), {ID::A, ID::B, ID::C}, {ID::Y}, features);
-		setup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, features);
+		setup_type(ID($lcu), {TW::P, TW::G, TW::CI}, {TW::CO}, features);
+		setup_type(ID($alu), {TW::A, TW::B, TW::CI, TW::BI}, {TW::X, TW::Y, TW::CO}, features);
+		setup_type(ID($macc_v2), {TW::A, TW::B, TW::C}, {TW::Y}, features);
+		setup_type(ID($fa), {TW::A, TW::B, TW::C}, {TW::X, TW::Y}, features);
 	}
 	constexpr void setup_internals_ff()
 	{
 		Features features {};
 		features.is_ff = true;
-		setup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q}, features);
-		setup_type(ID($ff), {ID::D}, {ID::Q}, features);
-		setup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q}, features);
-		setup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q}, features);
-		setup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q}, features);
-		setup_type(ID($dffsre), {ID::CLK, ID::SET, ID::CLR, ID::D, ID::EN}, {ID::Q}, features);
-		setup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q}, features);
-		setup_type(ID($adffe), {ID::CLK, ID::ARST, ID::D, ID::EN}, {ID::Q}, features);
-		setup_type(ID($aldff), {ID::CLK, ID::ALOAD, ID::AD, ID::D}, {ID::Q}, features);
-		setup_type(ID($aldffe), {ID::CLK, ID::ALOAD, ID::AD, ID::D, ID::EN}, {ID::Q}, features);
-		setup_type(ID($sdff), {ID::CLK, ID::SRST, ID::D}, {ID::Q}, features);
-		setup_type(ID($sdffe), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q}, features);
-		setup_type(ID($sdffce), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q}, features);
-		setup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q}, features);
-		setup_type(ID($adlatch), {ID::EN, ID::D, ID::ARST}, {ID::Q}, features);
-		setup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q}, features);
+		setup_type(ID($sr), {TW::SET, TW::CLR}, {TW::Q}, features);
+		setup_type(ID($ff), {TW::D}, {TW::Q}, features);
+		setup_type(ID($dff), {TW::CLK, TW::D}, {TW::Q}, features);
+		setup_type(ID($dffe), {TW::CLK, TW::EN, TW::D}, {TW::Q}, features);
+		setup_type(ID($dffsr), {TW::CLK, TW::SET, TW::CLR, TW::D}, {TW::Q}, features);
+		setup_type(ID($dffsre), {TW::CLK, TW::SET, TW::CLR, TW::D, TW::EN}, {TW::Q}, features);
+		setup_type(ID($adff), {TW::CLK, TW::ARST, TW::D}, {TW::Q}, features);
+		setup_type(ID($adffe), {TW::CLK, TW::ARST, TW::D, TW::EN}, {TW::Q}, features);
+		setup_type(ID($aldff), {TW::CLK, TW::ALOAD, TW::AD, TW::D}, {TW::Q}, features);
+		setup_type(ID($aldffe), {TW::CLK, TW::ALOAD, TW::AD, TW::D, TW::EN}, {TW::Q}, features);
+		setup_type(ID($sdff), {TW::CLK, TW::SRST, TW::D}, {TW::Q}, features);
+		setup_type(ID($sdffe), {TW::CLK, TW::SRST, TW::D, TW::EN}, {TW::Q}, features);
+		setup_type(ID($sdffce), {TW::CLK, TW::SRST, TW::D, TW::EN}, {TW::Q}, features);
+		setup_type(ID($dlatch), {TW::EN, TW::D}, {TW::Q}, features);
+		setup_type(ID($adlatch), {TW::EN, TW::D, TW::ARST}, {TW::Q}, features);
+		setup_type(ID($dlatchsr), {TW::EN, TW::SET, TW::CLR, TW::D}, {TW::Q}, features);
 	}
 	constexpr void setup_internals_anyinit()
 	{
 		Features features {};
 		features.is_anyinit = true;
-		setup_type(ID($anyinit), {ID::D}, {ID::Q}, features);
+		setup_type(ID($anyinit), {TW::D}, {TW::Q}, features);
 	}
 	constexpr void setup_internals_mem_noff()
 	{
@@ -163,24 +163,24 @@ struct CellTableBuilder {
 		features.is_mem_noff = true;
 		// NOT setup_internals_ff()
 
-		setup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA}, features);
-		setup_type(ID($memrd_v2), {ID::CLK, ID::EN, ID::ARST, ID::SRST, ID::ADDR}, {ID::DATA}, features);
-		setup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, {}, features);
-		setup_type(ID($memwr_v2), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, {}, features);
-		setup_type(ID($meminit), {ID::ADDR, ID::DATA}, {}, features);
-		setup_type(ID($meminit_v2), {ID::ADDR, ID::DATA, ID::EN}, {}, features);
-		setup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA}, features);
-		setup_type(ID($mem_v2), {ID::RD_CLK, ID::RD_EN, ID::RD_ARST, ID::RD_SRST, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA}, features);
+		setup_type(ID($memrd), {TW::CLK, TW::EN, TW::ADDR}, {TW::DATA}, features);
+		setup_type(ID($memrd_v2), {TW::CLK, TW::EN, TW::ARST, TW::SRST, TW::ADDR}, {TW::DATA}, features);
+		setup_type(ID($memwr), {TW::CLK, TW::EN, TW::ADDR, TW::DATA}, {}, features);
+		setup_type(ID($memwr_v2), {TW::CLK, TW::EN, TW::ADDR, TW::DATA}, {}, features);
+		setup_type(ID($meminit), {TW::ADDR, TW::DATA}, {}, features);
+		setup_type(ID($meminit_v2), {TW::ADDR, TW::DATA, TW::EN}, {}, features);
+		setup_type(ID($mem), {TW::RD_CLK, TW::RD_EN, TW::RD_ADDR, TW::WR_CLK, TW::WR_EN, TW::WR_ADDR, TW::WR_DATA}, {TW::RD_DATA}, features);
+		setup_type(ID($mem_v2), {TW::RD_CLK, TW::RD_EN, TW::RD_ARST, TW::RD_SRST, TW::RD_ADDR, TW::WR_CLK, TW::WR_EN, TW::WR_ADDR, TW::WR_DATA}, {TW::RD_DATA}, features);
 
 		// What?
-		setup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT}, features);
+		setup_type(ID($fsm), {TW::CLK, TW::ARST, TW::CTRL_IN}, {TW::CTRL_OUT}, features);
 	}
 	constexpr void setup_stdcells_tristate()
 	{
 		Features features {};
 		features.is_stdcell = true;
 		features.is_tristate = true;
-		setup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, features);
+		setup_type(ID($_TBUF_), {TW::A, TW::E}, {TW::Y}, features);
 	}
 
 	constexpr void setup_stdcells_eval()
@@ -188,25 +188,25 @@ struct CellTableBuilder {
 		Features features {};
 		features.is_stdcell = true;
 		features.is_evaluable = true;
-		setup_type(ID($_BUF_), {ID::A}, {ID::Y}, features);
-		setup_type(ID($_NOT_), {ID::A}, {ID::Y}, features);
-		setup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, features);
-		setup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, features);
-		setup_type(ID($_OR_),  {ID::A, ID::B}, {ID::Y}, features);
-		setup_type(ID($_NOR_),  {ID::A, ID::B}, {ID::Y}, features);
-		setup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, features);
-		setup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, features);
-		setup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, features);
-		setup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, features);
-		setup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, features);
-		setup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, features);
-		setup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, features);
-		setup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, features);
-		setup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, features);
-		setup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, features);
-		setup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, features);
-		setup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, features);
-		setup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, features);
+		setup_type(ID($_BUF_), {TW::A}, {TW::Y}, features);
+		setup_type(ID($_NOT_), {TW::A}, {TW::Y}, features);
+		setup_type(ID($_AND_), {TW::A, TW::B}, {TW::Y}, features);
+		setup_type(ID($_NAND_), {TW::A, TW::B}, {TW::Y}, features);
+		setup_type(ID($_OR_),  {TW::A, TW::B}, {TW::Y}, features);
+		setup_type(ID($_NOR_),  {TW::A, TW::B}, {TW::Y}, features);
+		setup_type(ID($_XOR_), {TW::A, TW::B}, {TW::Y}, features);
+		setup_type(ID($_XNOR_), {TW::A, TW::B}, {TW::Y}, features);
+		setup_type(ID($_ANDNOT_), {TW::A, TW::B}, {TW::Y}, features);
+		setup_type(ID($_ORNOT_), {TW::A, TW::B}, {TW::Y}, features);
+		setup_type(ID($_MUX_), {TW::A, TW::B, TW::S}, {TW::Y}, features);
+		setup_type(ID($_NMUX_), {TW::A, TW::B, TW::S}, {TW::Y}, features);
+		setup_type(ID($_MUX4_), {TW::A, TW::B, TW::C, TW::D, TW::S, TW::T}, {TW::Y}, features);
+		setup_type(ID($_MUX8_), {TW::A, TW::B, TW::C, TW::D, TW::E, TW::F, TW::G, TW::H, TW::S, TW::T, TW::U}, {TW::Y}, features);
+		setup_type(ID($_MUX16_), {TW::A, TW::B, TW::C, TW::D, TW::E, TW::F, TW::G, TW::H, TW::I, TW::J, TW::K, TW::L, TW::M, TW::N, TW::O, TW::P, TW::S, TW::T, TW::U, TW::V}, {TW::Y}, features);
+		setup_type(ID($_AOI3_), {TW::A, TW::B, TW::C}, {TW::Y}, features);
+		setup_type(ID($_OAI3_), {TW::A, TW::B, TW::C}, {TW::Y}, features);
+		setup_type(ID($_AOI4_), {TW::A, TW::B, TW::C, TW::D}, {TW::Y}, features);
+		setup_type(ID($_OAI4_), {TW::A, TW::B, TW::C, TW::D}, {TW::Y}, features);
 	}
 
 	constexpr void setup_stdcells_ff() {
@@ -216,194 +216,194 @@ struct CellTableBuilder {
 
 		// for (auto c1 : list_np)
 		// for (auto c2 : list_np)
-		// 	setup_type(std::string("$_SR_") + c1 + c2 + "_", {ID::S, ID::R}, {ID::Q}, features);
-		setup_type(ID($_SR_NN_), {ID::S, ID::R}, {ID::Q}, features);
-		setup_type(ID($_SR_NP_), {ID::S, ID::R}, {ID::Q}, features);
-		setup_type(ID($_SR_PN_), {ID::S, ID::R}, {ID::Q}, features);
-		setup_type(ID($_SR_PP_), {ID::S, ID::R}, {ID::Q}, features);
+		// 	setup_type(std::string("$_SR_") + c1 + c2 + "_", {TW::S, TW::R}, {TW::Q}, features);
+		setup_type(ID($_SR_NN_), {TW::S, TW::R}, {TW::Q}, features);
+		setup_type(ID($_SR_NP_), {TW::S, TW::R}, {TW::Q}, features);
+		setup_type(ID($_SR_PN_), {TW::S, TW::R}, {TW::Q}, features);
+		setup_type(ID($_SR_PP_), {TW::S, TW::R}, {TW::Q}, features);
 
-		setup_type(ID($_FF_), {ID::D}, {ID::Q}, features);
+		setup_type(ID($_FF_), {TW::D}, {TW::Q}, features);
 
 		// for (auto c1 : list_np)
-		// 	setup_type(std::string("$_DFF_") + c1 + "_", {ID::C, ID::D}, {ID::Q}, features);
-		setup_type(ID::$_DFF_N_, {ID::C, ID::D}, {ID::Q}, features);
-		setup_type(ID::$_DFF_P_, {ID::C, ID::D}, {ID::Q}, features);
+		// 	setup_type(std::string("$_DFF_") + c1 + "_", {TW::C, TW::D}, {TW::Q}, features);
+		setup_type(ID::$_DFF_N_, {TW::C, TW::D}, {TW::Q}, features);
+		setup_type(ID::$_DFF_P_, {TW::C, TW::D}, {TW::Q}, features);
 
 		// for (auto c1 : list_np)
 		// for (auto c2 : list_np)
-		// 	setup_type(std::string("$_DFFE_") + c1 + c2 + "_", {ID::C, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID::$_DFFE_NN_, {ID::C, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID::$_DFFE_NP_, {ID::C, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID::$_DFFE_PN_, {ID::C, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID::$_DFFE_PP_, {ID::C, ID::D, ID::E}, {ID::Q}, features);
+		// 	setup_type(std::string("$_DFFE_") + c1 + c2 + "_", {TW::C, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID::$_DFFE_NN_, {TW::C, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID::$_DFFE_NP_, {TW::C, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID::$_DFFE_PN_, {TW::C, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID::$_DFFE_PP_, {TW::C, TW::D, TW::E}, {TW::Q}, features);
 		// for (auto c1 : list_np)
 		// for (auto c2 : list_np)
 		// for (auto c3 : list_01)
-		// 	setup_type(std::string("$_DFF_") + c1 + c2 + c3 + "_", {ID::C, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DFF_NN0_), {ID::C, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DFF_NN1_), {ID::C, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DFF_NP0_), {ID::C, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DFF_NP1_), {ID::C, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DFF_PN0_), {ID::C, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DFF_PN1_), {ID::C, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DFF_PP0_), {ID::C, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DFF_PP1_), {ID::C, ID::R, ID::D}, {ID::Q}, features);
+		// 	setup_type(std::string("$_DFF_") + c1 + c2 + c3 + "_", {TW::C, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DFF_NN0_), {TW::C, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DFF_NN1_), {TW::C, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DFF_NP0_), {TW::C, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DFF_NP1_), {TW::C, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DFF_PN0_), {TW::C, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DFF_PN1_), {TW::C, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DFF_PP0_), {TW::C, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DFF_PP1_), {TW::C, TW::R, TW::D}, {TW::Q}, features);
 		// for (auto c1 : list_np)
 		// for (auto c2 : list_np)
 		// for (auto c3 : list_01)
 		// for (auto c4 : list_np)
-		// 	setup_type(std::string("$_DFFE_") + c1 + c2 + c3 + c4 + "_", {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFE_NN0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFE_NN0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFE_NN1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFE_NN1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFE_NP0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFE_NP0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFE_NP1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFE_NP1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFE_PN0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFE_PN0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFE_PN1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFE_PN1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFE_PP0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFE_PP0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFE_PP1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFE_PP1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
+		// 	setup_type(std::string("$_DFFE_") + c1 + c2 + c3 + c4 + "_", {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFE_NN0N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFE_NN0P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFE_NN1N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFE_NN1P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFE_NP0N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFE_NP0P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFE_NP1N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFE_NP1P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFE_PN0N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFE_PN0P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFE_PN1N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFE_PN1P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFE_PP0N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFE_PP0P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFE_PP1N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFE_PP1P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
 		// for (auto c1 : list_np)
 		// for (auto c2 : list_np)
-		// 	setup_type(std::string("$_ALDFF_") + c1 + c2 + "_", {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features);
-		setup_type(ID($_ALDFF_NN_), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features);
-		setup_type(ID($_ALDFF_NP_), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features);
-		setup_type(ID($_ALDFF_PN_), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features);
-		setup_type(ID($_ALDFF_PP_), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q}, features);
+		// 	setup_type(std::string("$_ALDFF_") + c1 + c2 + "_", {TW::C, TW::L, TW::AD, TW::D}, {TW::Q}, features);
+		setup_type(ID($_ALDFF_NN_), {TW::C, TW::L, TW::AD, TW::D}, {TW::Q}, features);
+		setup_type(ID($_ALDFF_NP_), {TW::C, TW::L, TW::AD, TW::D}, {TW::Q}, features);
+		setup_type(ID($_ALDFF_PN_), {TW::C, TW::L, TW::AD, TW::D}, {TW::Q}, features);
+		setup_type(ID($_ALDFF_PP_), {TW::C, TW::L, TW::AD, TW::D}, {TW::Q}, features);
 		// for (auto c1 : list_np)
 		// for (auto c2 : list_np)
 		// for (auto c3 : list_np)
-		// 	setup_type(std::string("$_ALDFFE_") + c1 + c2 + c3 + "_", {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_ALDFFE_NNN_), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_ALDFFE_NNP_), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_ALDFFE_NPN_), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_ALDFFE_NPP_), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_ALDFFE_PNN_), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_ALDFFE_PNP_), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_ALDFFE_PPN_), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_ALDFFE_PPP_), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q}, features);
+		// 	setup_type(std::string("$_ALDFFE_") + c1 + c2 + c3 + "_", {TW::C, TW::L, TW::AD, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_ALDFFE_NNN_), {TW::C, TW::L, TW::AD, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_ALDFFE_NNP_), {TW::C, TW::L, TW::AD, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_ALDFFE_NPN_), {TW::C, TW::L, TW::AD, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_ALDFFE_NPP_), {TW::C, TW::L, TW::AD, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_ALDFFE_PNN_), {TW::C, TW::L, TW::AD, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_ALDFFE_PNP_), {TW::C, TW::L, TW::AD, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_ALDFFE_PPN_), {TW::C, TW::L, TW::AD, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_ALDFFE_PPP_), {TW::C, TW::L, TW::AD, TW::D, TW::E}, {TW::Q}, features);
 		// for (auto c1 : list_np)
 		// for (auto c2 : list_np)
 		// for (auto c3 : list_np)
-		// 	setup_type(std::string("$_DFFSR_") + c1 + c2 + c3 + "_", {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DFFSR_NNN_), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DFFSR_NNP_), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DFFSR_NPN_), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DFFSR_NPP_), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DFFSR_PNN_), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DFFSR_PNP_), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DFFSR_PPN_), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DFFSR_PPP_), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}, features);
+		// 	setup_type(std::string("$_DFFSR_") + c1 + c2 + c3 + "_", {TW::C, TW::S, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DFFSR_NNN_), {TW::C, TW::S, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DFFSR_NNP_), {TW::C, TW::S, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DFFSR_NPN_), {TW::C, TW::S, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DFFSR_NPP_), {TW::C, TW::S, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DFFSR_PNN_), {TW::C, TW::S, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DFFSR_PNP_), {TW::C, TW::S, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DFFSR_PPN_), {TW::C, TW::S, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DFFSR_PPP_), {TW::C, TW::S, TW::R, TW::D}, {TW::Q}, features);
 		// for (auto c1 : list_np)
 		// for (auto c2 : list_np)
 		// for (auto c3 : list_np)
 		// for (auto c4 : list_np)
-		// 	setup_type(std::string("$_DFFSRE_") + c1 + c2 + c3 + c4 + "_", {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFSRE_NNNN_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFSRE_NNNP_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFSRE_NNPN_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFSRE_NNPP_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFSRE_NPNN_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFSRE_NPNP_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFSRE_NPPN_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFSRE_NPPP_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFSRE_PNNN_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFSRE_PNNP_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFSRE_PNPN_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFSRE_PNPP_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFSRE_PPNN_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFSRE_PPNP_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFSRE_PPPN_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_DFFSRE_PPPP_), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q}, features);
+		// 	setup_type(std::string("$_DFFSRE_") + c1 + c2 + c3 + c4 + "_", {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFSRE_NNNN_), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFSRE_NNNP_), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFSRE_NNPN_), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFSRE_NNPP_), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFSRE_NPNN_), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFSRE_NPNP_), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFSRE_NPPN_), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFSRE_NPPP_), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFSRE_PNNN_), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFSRE_PNNP_), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFSRE_PNPN_), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFSRE_PNPP_), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFSRE_PPNN_), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFSRE_PPNP_), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFSRE_PPPN_), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_DFFSRE_PPPP_), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q}, features);
 		// for (auto c1 : list_np)
 		// for (auto c2 : list_np)
 		// for (auto c3 : list_01)
-		// 	setup_type(std::string("$_SDFF_") + c1 + c2 + c3 + "_", {ID::C, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_SDFF_NN0_), {ID::C, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_SDFF_NN1_), {ID::C, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_SDFF_NP0_), {ID::C, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_SDFF_NP1_), {ID::C, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_SDFF_PN0_), {ID::C, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_SDFF_PN1_), {ID::C, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_SDFF_PP0_), {ID::C, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_SDFF_PP1_), {ID::C, ID::R, ID::D}, {ID::Q}, features);
+		// 	setup_type(std::string("$_SDFF_") + c1 + c2 + c3 + "_", {TW::C, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_SDFF_NN0_), {TW::C, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_SDFF_NN1_), {TW::C, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_SDFF_NP0_), {TW::C, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_SDFF_NP1_), {TW::C, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_SDFF_PN0_), {TW::C, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_SDFF_PN1_), {TW::C, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_SDFF_PP0_), {TW::C, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_SDFF_PP1_), {TW::C, TW::R, TW::D}, {TW::Q}, features);
 		// for (auto c1 : list_np)
 		// for (auto c2 : list_np)
 		// for (auto c3 : list_01)
 		// for (auto c4 : list_np)
-		// 	setup_type(std::string("$_SDFFE_") + c1 + c2 + c3 + c4 + "_", {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFE_NN0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFE_NN0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFE_NN1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFE_NN1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFE_NP0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFE_NP0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFE_NP1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFE_NP1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFE_PN0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFE_PN0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFE_PN1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFE_PN1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFE_PP0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFE_PP0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFE_PP1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFE_PP1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
+		// 	setup_type(std::string("$_SDFFE_") + c1 + c2 + c3 + c4 + "_", {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFE_NN0N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFE_NN0P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFE_NN1N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFE_NN1P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFE_NP0N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFE_NP0P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFE_NP1N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFE_NP1P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFE_PN0N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFE_PN0P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFE_PN1N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFE_PN1P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFE_PP0N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFE_PP0P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFE_PP1N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFE_PP1P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
 		// for (auto c1 : list_np)
 		// for (auto c2 : list_np)
 		// for (auto c3 : list_01)
 		// for (auto c4 : list_np)
-		// 	setup_type(std::string("$_SDFFCE_") + c1 + c2 + c3 + c4 + "_", {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFCE_NN0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFCE_NN0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFCE_NN1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFCE_NN1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFCE_NP0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFCE_NP0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFCE_NP1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFCE_NP1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFCE_PN0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFCE_PN0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFCE_PN1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFCE_PN1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFCE_PP0N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFCE_PP0P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFCE_PP1N_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
-		setup_type(ID($_SDFFCE_PP1P_), {ID::C, ID::R, ID::D, ID::E}, {ID::Q}, features);
+		// 	setup_type(std::string("$_SDFFCE_") + c1 + c2 + c3 + c4 + "_", {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFCE_NN0N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFCE_NN0P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFCE_NN1N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFCE_NN1P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFCE_NP0N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFCE_NP0P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFCE_NP1N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFCE_NP1P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFCE_PN0N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFCE_PN0P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFCE_PN1N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFCE_PN1P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFCE_PP0N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFCE_PP0P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFCE_PP1N_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
+		setup_type(ID($_SDFFCE_PP1P_), {TW::C, TW::R, TW::D, TW::E}, {TW::Q}, features);
 		// for (auto c1 : list_np)
-		// 	setup_type(std::string("$_DLATCH_") + c1 + "_", {ID::E, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCH_N_), {ID::E, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCH_P_), {ID::E, ID::D}, {ID::Q}, features);
+		// 	setup_type(std::string("$_DLATCH_") + c1 + "_", {TW::E, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCH_N_), {TW::E, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCH_P_), {TW::E, TW::D}, {TW::Q}, features);
 
 		// for (auto c1 : list_np)
 		// for (auto c2 : list_np)
 		// for (auto c3 : list_01)
-		// 	setup_type(std::string("$_DLATCH_") + c1 + c2 + c3 + "_", {ID::E, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCH_NN0_), {ID::E, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCH_NN1_), {ID::E, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCH_NP0_), {ID::E, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCH_NP1_), {ID::E, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCH_PN0_), {ID::E, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCH_PN1_), {ID::E, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCH_PP0_), {ID::E, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCH_PP1_), {ID::E, ID::R, ID::D}, {ID::Q}, features);
+		// 	setup_type(std::string("$_DLATCH_") + c1 + c2 + c3 + "_", {TW::E, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCH_NN0_), {TW::E, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCH_NN1_), {TW::E, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCH_NP0_), {TW::E, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCH_NP1_), {TW::E, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCH_PN0_), {TW::E, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCH_PN1_), {TW::E, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCH_PP0_), {TW::E, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCH_PP1_), {TW::E, TW::R, TW::D}, {TW::Q}, features);
 		// for (auto c1 : list_np)
 		// for (auto c2 : list_np)
 		// for (auto c3 : list_np)
-		// 	setup_type(std::string("$_DLATCHSR_") + c1 + c2 + c3 + "_", {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCHSR_NNN_), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCHSR_NNP_), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCHSR_NPN_), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCHSR_NPP_), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCHSR_PNN_), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCHSR_PNP_), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCHSR_PPN_), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features);
-		setup_type(ID($_DLATCHSR_PPP_), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}, features);
+		// 	setup_type(std::string("$_DLATCHSR_") + c1 + c2 + c3 + "_", {TW::E, TW::S, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCHSR_NNN_), {TW::E, TW::S, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCHSR_NNP_), {TW::E, TW::S, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCHSR_NPN_), {TW::E, TW::S, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCHSR_NPP_), {TW::E, TW::S, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCHSR_PNN_), {TW::E, TW::S, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCHSR_PNP_), {TW::E, TW::S, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCHSR_PPN_), {TW::E, TW::S, TW::R, TW::D}, {TW::Q}, features);
+		setup_type(ID($_DLATCHSR_PPP_), {TW::E, TW::S, TW::R, TW::D}, {TW::Q}, features);
 	}
 	constexpr CellTableBuilder() {
 		setup_internals_other();
@@ -583,7 +583,7 @@ struct NewCellTypes {
 
 	void setup_module(RTLIL::Module *module) {
 		pool<RTLIL::IdString> inputs, outputs;
-		for (RTLIL::IdString wire_name : module->ports) {
+		for (auto wire_name : module->ports) {
 			RTLIL::Wire *wire = module->wire(wire_name);
 			if (wire->port_input)
 				inputs.insert(wire->name);
@@ -607,7 +607,7 @@ struct NewCellTypes {
 		return static_cell_types(type) || custom_cell_types.count(type) != 0;
 	}
 
-	bool cell_output(const RTLIL::IdString &type, const RTLIL::IdString &port) const
+	bool cell_output(const RTLIL::IdString &type, TwineRef port) const
 	{
 		if (static_cell_types(type) && StaticCellTypes::port_info.outputs(type).contains(port)) {
 			return true;
@@ -616,7 +616,7 @@ struct NewCellTypes {
 		return it != custom_cell_types.end() && it->second.outputs.count(port) != 0;
 	}
 
-	bool cell_input(const RTLIL::IdString &type, const RTLIL::IdString &port) const
+	bool cell_input(const RTLIL::IdString &type, TwineRef port) const
 	{
 		if (static_cell_types(type) && StaticCellTypes::port_info.inputs(type).contains(port)) {
 			return true;
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 252a2bd14..b20e1d829 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -150,7 +150,7 @@ struct IdStringCollector {
 	IdStringCollector(std::vector<MonotonicFlag> &live_ids)
 			: live_ids(live_ids) {}
 
-	void trace(Twine::Id id) {
+	void trace(TwineRef id) {
 		// live_twines.push_back(id );
 		// TODO
 	}
@@ -265,7 +265,7 @@ void RTLIL::OwningIdString::collect_garbage()
 	for (auto &[idx, design] : *RTLIL::Design::get_all_designs()) {
 		for (RTLIL::Module *module : design->modules()) {
 			collectors[0].trace_keys(module->attributes);
-			// collectors[0].trace(Twine::Id(module->name));
+			// collectors[0].trace(TwineRef(module->name));
 			// TODO
 			ParallelDispatchThreadPool::Subpool subpool(thread_pool, ThreadPool::work_pool_size(0, module->cells_size(), 1000));
 			subpool.run([&collectors, module](const ParallelDispatchThreadPool::RunCtx &ctx) {
@@ -972,7 +972,7 @@ string RTLIL::AttrObject::get_string_attribute(IdString id) const
 	return value;
 }
 
-void RTLIL::Design::obj_set_src_id(RTLIL::AttrObject *obj, Twine::Id id)
+void RTLIL::Design::obj_set_src_id(RTLIL::AttrObject *obj, TwineRef id)
 {
 	if (obj->meta_ == nullptr) {
 		if (id == Twine::Null)
@@ -982,11 +982,11 @@ void RTLIL::Design::obj_set_src_id(RTLIL::AttrObject *obj, Twine::Id id)
 	ObjMeta &m = *obj->meta_;
 	if (m.src == id)
 		return;
-	if (m.src != Twine::Null)
-		twines.release(m.src);
+	// if (m.src != Twine::Null)
+	// 	twines.release(m.src);
 	m.src = id;
-	if (m.src != Twine::Null)
-		twines.retain(m.src);
+	// if (m.src != Twine::Null)
+	// 	twines.retain(m.src);
 	if (m.src == Twine::Null && m.name_id == Twine::Null) {
 		free_obj_meta(obj->meta_);
 		obj->meta_ = nullptr;
@@ -999,7 +999,7 @@ void RTLIL::Design::obj_release_src(RTLIL::AttrObject *obj)
 		return;
 	ObjMeta &m = *obj->meta_;
 	if (m.src != Twine::Null) {
-		twines.release(m.src);
+		// twines.release(m.src);
 		m.src = Twine::Null;
 	}
 	if (m.name_id == Twine::Null) {
@@ -1008,7 +1008,7 @@ void RTLIL::Design::obj_release_src(RTLIL::AttrObject *obj)
 	}
 }
 
-// void RTLIL::Design::obj_set_name(RTLIL::AttrObject *obj, Twine::Id name)
+// void RTLIL::Design::obj_set_name(RTLIL::AttrObject *obj, TwineRef name)
 // {
 // 	if (obj->meta_ == nullptr) {
 // 		if (name.empty())
@@ -1028,14 +1028,14 @@ void RTLIL::Design::obj_release_name(RTLIL::AttrObject *obj)
 	if (obj->meta_ == nullptr)
 		return;
 	ObjMeta &m = *obj->meta_;
-	m.name_id = Twine::Id();
+	m.name_id = TwineRef();
 	if (m.src == Twine::Null && m.name_id == Twine::Null) {
 		free_obj_meta(obj->meta_);
 		obj->meta_ = nullptr;
 	}
 }
 
-void RTLIL::Design::obj_set_name_id(RTLIL::AttrObject *obj, Twine::Id id)
+void RTLIL::Design::obj_set_name_id(RTLIL::AttrObject *obj, TwineRef id)
 {
 	if (obj->meta_ == nullptr) {
 		if (id == Twine::Null)
@@ -1045,11 +1045,11 @@ void RTLIL::Design::obj_set_name_id(RTLIL::AttrObject *obj, Twine::Id id)
 	ObjMeta &m = *obj->meta_;
 	if (m.name_id == id)
 		return;
-	if (m.name_id != Twine::Null)
-		twines.release(m.name_id);
+	// if (m.name_id != Twine::Null)
+	// 	twines.release(m.name_id);
 	m.name_id = id;
-	if (m.name_id != Twine::Null)
-		twines.retain(m.name_id);
+	// if (m.name_id != Twine::Null)
+	// 	twines.retain(m.name_id);
 	if (m.name_id == Twine::Null && m.src == Twine::Null) {
 		free_obj_meta(obj->meta_);
 		obj->meta_ = nullptr;
@@ -1077,7 +1077,7 @@ void RTLIL::Design::set_src_attribute(RTLIL::AttrObject *obj, const RTLIL::SrcAt
 		obj_set_src_id(obj, Twine::Null);
 		return;
 	}
-	Twine::Id new_id = Twine::Null;
+	TwineRef new_id = Twine::Null;
 	if (src.id != Twine::Null) {
 		// Direct id form — the caller is responsible for keeping the
 		// slot alive while we retain. obj_set_src_id handles retain.
@@ -1102,7 +1102,7 @@ void RTLIL::Design::set_src_attribute(RTLIL::AttrObject *obj, const RTLIL::SrcAt
 
 std::string RTLIL::Design::get_src_attribute(const RTLIL::AttrObject *obj) const
 {
-	return twines.flatten(obj_src_id(obj));
+	return twines.flat_string(obj_src_id(obj));
 }
 
 void RTLIL::Design::adopt_src_from(RTLIL::AttrObject *obj, const RTLIL::AttrObject *source)
@@ -1122,7 +1122,7 @@ void RTLIL::Design::adopt_src_from(RTLIL::AttrObject *obj,
 	// our pool. Cross-pool adoption goes through copy_src_into directly
 	// (taking a src Design*), since AttrObject is not polymorphic and
 	// we can't downcast to recover the source design from here.
-	Twine::Id source_id = obj_src_id(source);
+	TwineRef source_id = obj_src_id(source);
 	obj_set_src_id(obj, source_id);
 }
 
@@ -1146,7 +1146,7 @@ namespace {
 	{
 		if (!src || !src_design || !dst_design)
 			return;
-		Twine::Id src_id = src_design->obj_src_id(src);
+		TwineRef src_id = src_design->obj_src_id(src);
 		if (src_id == Twine::Null) {
 			dst_design->obj_set_src_id(dst, Twine::Null);
 			return;
@@ -1155,7 +1155,7 @@ namespace {
 			dst_design->obj_set_src_id(dst, src_id);
 			return;
 		}
-		Twine::Id new_id = dst_design->twines.copy_from(src_design->twines, src_id);
+		TwineRef new_id = dst_design->twines.copy_from(src_design->twines, src_id);
 		dst_design->obj_set_src_id(dst, new_id);
 		dst_design->twines.release(new_id);
 	}
@@ -1183,33 +1183,33 @@ void RTLIL::Design::free_obj_meta(RTLIL::ObjMeta *m)
 
 void RTLIL::Design::merge_src(RTLIL::AttrObject *target, const RTLIL::AttrObject *source)
 {
-	std::vector<Twine::Id> ids;
-	Twine::Id tgt_id = obj_src_id(target);
+	std::vector<TwineRef> ids;
+	TwineRef tgt_id = obj_src_id(target);
 	if (tgt_id != Twine::Null)
 		ids.push_back(tgt_id);
 	if (source) {
-		Twine::Id src_id = obj_src_id(source);
+		TwineRef src_id = obj_src_id(source);
 		if (src_id != Twine::Null)
 			ids.push_back(src_id);
 	}
 	if (ids.empty())
 		return;
-	Twine::Id merged = twines.concat(std::span<const Twine::Id>{ids});
+	TwineRef merged = twines.concat(std::span<const TwineRef>{ids});
 	obj_set_src_id(target, merged);
 	twines.release(merged);
 }
 
 void RTLIL::Design::merge_src(RTLIL::AttrObject *target, const pool<std::string> &leaves)
 {
-	std::vector<Twine::Id> ids;
-	std::vector<Twine::Id> temp_interns;
-	Twine::Id tgt_id = obj_src_id(target);
+	std::vector<TwineRef> ids;
+	std::vector<TwineRef> temp_interns;
+	TwineRef tgt_id = obj_src_id(target);
 	if (tgt_id != Twine::Null)
 		ids.push_back(tgt_id);
 	for (const auto &leaf : leaves) {
 		if (leaf.empty())
 			continue;
-		Twine::Id leaf_id = twines.get_ref(leaf);
+		TwineRef leaf_id = twines.get_ref(leaf);
 		if (leaf_id == Twine::Null) {
 			leaf_id = twines.intern(leaf);
 			temp_interns.push_back(leaf_id);
@@ -1218,10 +1218,10 @@ void RTLIL::Design::merge_src(RTLIL::AttrObject *target, const pool<std::string>
 	}
 	if (ids.empty())
 		return;
-	Twine::Id merged = twines.concat(std::span<const Twine::Id>{ids});
+	TwineRef merged = twines.concat(std::span<const TwineRef>{ids});
 	obj_set_src_id(target, merged);
 	twines.release(merged);
-	for (Twine::Id id : temp_interns)
+	for (TwineRef id : temp_interns)
 		twines.release(id);
 }
 
@@ -1266,16 +1266,16 @@ size_t RTLIL::Design::gc_twines()
 		return 0;
 
 	// Mark phase: every live src_id on any AttrObject is a root.
-	pool<Twine::Id> live;
+	pool<TwineRef> live;
 	walk_attr_objects(this, [&](const RTLIL::AttrObject *obj) {
-		Twine::Id id = obj_src_id(obj);
+		TwineRef id = obj_src_id(obj);
 		if (id != Twine::Null)
 			live.insert(id);
 	});
 
 	// Sweep + compact: rebuild the pool keeping only reachable nodes,
 	// receiving an old-id -> new-id remap.
-	dict<Twine::Id, Twine::Id> remap = twines.gc(live);
+	dict<TwineRef, TwineRef> remap = twines.gc(live);
 
 	// Rewrite every meta-vector src_id through the remap. The pool was
 	// rebuilt, so the old ids no longer mean anything — we update the
@@ -1305,7 +1305,7 @@ size_t RTLIL::Design::gc_twines()
 pool<std::string> RTLIL::Design::src_leaves(const RTLIL::AttrObject *obj) const
 {
 	pool<std::string> result;
-	Twine::Id id = obj_src_id(obj);
+	TwineRef id = obj_src_id(obj);
 	if (id == Twine::Null)
 		return result;
 	const TwinePool *pool = &twines;
@@ -1314,7 +1314,7 @@ pool<std::string> RTLIL::Design::src_leaves(const RTLIL::AttrObject *obj) const
 		result.insert(pool->flat_string(id));
 	} else {
 		// Flat-children invariant: every concat child is a Leaf or Suffix.
-		for (Twine::Id c : n.children())
+		for (TwineRef c : n.children())
 			result.insert(pool->flat_string(c));
 	}
 	return result;
@@ -1398,7 +1398,7 @@ vector<int> RTLIL::AttrObject::get_intvec_attribute(IdString id) const
 	return data;
 }
 
-bool RTLIL::Selection::boxed_module(Twine::Id mod_name) const
+bool RTLIL::Selection::boxed_module(TwineRef mod_name) const
 {
 	if (current_design != nullptr) {
 		auto module = current_design->module(mod_name);
@@ -1410,7 +1410,7 @@ bool RTLIL::Selection::boxed_module(Twine::Id mod_name) const
 	}
 }
 
-bool RTLIL::Selection::selected_module(Twine::Id mod_name) const
+bool RTLIL::Selection::selected_module(TwineRef mod_name) const
 {
 	if (complete_selection)
 		return true;
@@ -1425,7 +1425,7 @@ bool RTLIL::Selection::selected_module(Twine::Id mod_name) const
 	return false;
 }
 
-bool RTLIL::Selection::selected_whole_module(Twine::Id mod_name) const
+bool RTLIL::Selection::selected_whole_module(TwineRef mod_name) const
 {
 	if (complete_selection)
 		return true;
@@ -1438,7 +1438,7 @@ bool RTLIL::Selection::selected_whole_module(Twine::Id mod_name) const
 	return false;
 }
 
-bool RTLIL::Selection::selected_member(Twine::Id mod_name, Twine::Id memb_name) const
+bool RTLIL::Selection::selected_member(TwineRef mod_name, TwineRef memb_name) const
 {
 	if (complete_selection)
 		return true;
@@ -1472,7 +1472,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
 		return;
 	}
 
-	std::vector<Twine::Id> del_list, add_list;
+	std::vector<TwineRef> del_list, add_list;
 
 	del_list.clear();
 	for (auto mod_name : selected_modules) {
@@ -1560,30 +1560,30 @@ std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
 	return &all_designs;
 }
 
-RTLIL::ObjRange<RTLIL::Module*, Twine::Id> RTLIL::Design::modules()
+RTLIL::ObjRange<RTLIL::Module*, TwineRef> RTLIL::Design::modules()
 {
-	return RTLIL::ObjRange<RTLIL::Module*, Twine::Id>(&modules_, &refcount_modules_);
+	return RTLIL::ObjRange<RTLIL::Module*, TwineRef>(&modules_, &refcount_modules_);
 }
 
+// RTLIL::Module *RTLIL::Design::module(IdString id) {
+// 	auto t = twines.lookup(id.c_str());
+// 	if (t)
+// 		return module(t);
+// 	return nullptr;
+// }
+
+const RTLIL::Module *RTLIL::Design::module(IdString id) const {
+	return modules_.count(id) ? modules_.at(id) : NULL;
+}
 RTLIL::Module *RTLIL::Design::module(IdString id) {
-	auto t = twines.lookup(id.c_str());
-	if (t)
-		return module(t);
-	return nullptr;
-}
-
-const RTLIL::Module *RTLIL::Design::module(Twine::Id id) const {
 	return modules_.count(id) ? modules_.at(id) : NULL;
 }
-RTLIL::Module *RTLIL::Design::module(Twine::Id id) {
-	return modules_.count(id) ? modules_.at(id) : NULL;
-}
-// RTLIL::Module *RTLIL::Design::module(Twine::Id name)
+// RTLIL::Module *RTLIL::Design::module(TwineRef name)
 // {
 // 	return modules_.count(name) ? modules_.at(name) : NULL;
 // }
 
-// const RTLIL::Module *RTLIL::Design::module(Twine::Id name) const
+// const RTLIL::Module *RTLIL::Design::module(TwineRef name) const
 // {
 // 	return modules_.count(name) ? modules_.at(name) : NULL;
 // }
@@ -1609,7 +1609,7 @@ void RTLIL::Design::add(RTLIL::Binding *binding)
 	bindings_.push_back(binding);
 }
 
-RTLIL::Module *RTLIL::Design::addModule(Twine::Id name)
+RTLIL::Module *RTLIL::Design::addModule(TwineRef name)
 {
 	if (modules_.count(name) != 0)
 		log_error("Attempted to add new module named '%s', but a module by that name already exists\n", name);
@@ -1712,7 +1712,7 @@ void RTLIL::Design::remove(RTLIL::Module *module)
 	delete module;
 }
 
-void RTLIL::Design::rename(RTLIL::Module *module, Twine::Id new_name)
+void RTLIL::Design::rename(RTLIL::Module *module, TwineRef new_name)
 {
 	modules_.erase(module->name);
 	module->meta_->name_id = new_name;
@@ -1770,21 +1770,21 @@ void RTLIL::Design::clone_into(RTLIL::Design *dst) const
 		it->second->clone(dst, /*src_id_verbatim=*/true);
 }
 
-bool RTLIL::Design::selected_module(Twine::Id mod_name) const
+bool RTLIL::Design::selected_module(TwineRef mod_name) const
 {
 	if (selected_active_module && mod_name != selected_active_module)
 		return false;
 	return selection().selected_module(mod_name);
 }
 
-bool RTLIL::Design::selected_whole_module(Twine::Id mod_name) const
+bool RTLIL::Design::selected_whole_module(TwineRef mod_name) const
 {
 	if (selected_active_module && mod_name != selected_active_module)
 		return false;
 	return selection().selected_whole_module(mod_name);
 }
 
-bool RTLIL::Design::selected_member(Twine::Id mod_name, Twine::Id memb_name) const
+bool RTLIL::Design::selected_member(TwineRef mod_name, TwineRef memb_name) const
 {
 	if (selected_active_module && mod_name != selected_active_module)
 		return false;
@@ -1932,14 +1932,14 @@ RTLIL::Module::~Module()
 #endif
 }
 
-Twine::Id RTLIL::Module::src_id() const
+TwineRef RTLIL::Module::src_id() const
 {
 	if (!design)
 		return Twine::Null;
 	return design->obj_src_id(this);
 }
 
-void RTLIL::Module::set_src_id(Twine::Id id)
+void RTLIL::Module::set_src_id(TwineRef id)
 {
 	log_assert(design && "Module::set_src_id requires the module to be attached to a design");
 	design->obj_set_src_id(this, id);
@@ -1965,7 +1965,7 @@ std::string RTLIL::Module::get_src_attribute() const
 	return design->get_src_attribute(this);
 }
 
-void RTLIL::Module::absorb_attrs(dict<Twine::Id, RTLIL::Const> &&buf)
+void RTLIL::Module::absorb_attrs(dict<TwineRef, RTLIL::Const> &&buf)
 {
 	log_assert(design && "Module::absorb_attrs requires the module to be attached to a design");
 	design->absorb_attrs(this, std::move(buf));
@@ -2005,7 +2005,7 @@ void RTLIL::Module::makeblackbox()
 	set_bool_attribute(ID::blackbox);
 }
 
-void RTLIL::Module::expand_interfaces(RTLIL::Design *, const dict<Twine::Id, RTLIL::Module *> &)
+void RTLIL::Module::expand_interfaces(RTLIL::Design *, const dict<TwineRef, RTLIL::Module *> &)
 {
 	log_error("Class doesn't support expand_interfaces (module: `%s')!\n", name.unescape());
 }
@@ -2015,24 +2015,24 @@ bool RTLIL::Module::reprocess_if_necessary(RTLIL::Design *)
 	return false;
 }
 
-Twine::Id RTLIL::Module::derive(RTLIL::Design*, const dict<Twine::Id, RTLIL::Const> &, bool mayfail)
+TwineRef RTLIL::Module::derive(RTLIL::Design*, const dict<TwineRef, RTLIL::Const> &, bool mayfail)
 {
 	if (mayfail)
-		return Twine::Id();
+		return TwineRef();
 	log_error("Module `%s' is used with parameters but is not parametric!\n", name.unescape());
 }
 
 
-Twine::Id RTLIL::Module::derive(RTLIL::Design*, const dict<Twine::Id, RTLIL::Const> &, const dict<Twine::Id, RTLIL::Module*> &, const dict<Twine::Id, Twine::Id> &, bool mayfail)
+TwineRef RTLIL::Module::derive(RTLIL::Design*, const dict<TwineRef, RTLIL::Const> &, const dict<TwineRef, RTLIL::Module*> &, const dict<TwineRef, TwineRef> &, bool mayfail)
 {
 	if (mayfail)
-		return Twine::Id();
+		return TwineRef();
 	log_error("Module `%s' is used with parameters but is not parametric!\n", name.unescape());
 }
 
-size_t RTLIL::Module::count_id(Twine::Id id)
+size_t RTLIL::Module::count_id(TwineRef id)
 {
-	Twine::Id tid = design->twines.lookup(id.str());
+	TwineRef tid = design->twines.lookup(id.str());
 	size_t n = memories.count(id) + processes.count(id);
 	if (tid != Twine::Null)
 		n += wires_.count(tid) + cells_.count(tid);
@@ -2045,7 +2045,7 @@ namespace {
 	{
 		const RTLIL::Module *module;
 		RTLIL::Cell *cell;
-		pool<Twine::Id> expected_params, expected_ports;
+		pool<TwineRef> expected_params, expected_ports;
 
 		InternalCellChecker(const RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
 
@@ -2059,7 +2059,7 @@ namespace {
 					cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
 		}
 
-		int param(Twine::Id name)
+		int param(TwineRef name)
 		{
 			auto it = cell->parameters.find(name);
 			if (it == cell->parameters.end())
@@ -2068,7 +2068,7 @@ namespace {
 			return it->second.as_int();
 		}
 
-		int param_bool(Twine::Id name)
+		int param_bool(TwineRef name)
 		{
 			int v = param(name);
 			if (GetSize(cell->parameters.at(name)) > 32)
@@ -2078,7 +2078,7 @@ namespace {
 			return v;
 		}
 
-		int param_bool(Twine::Id name, bool expected)
+		int param_bool(TwineRef name, bool expected)
 		{
 			int v = param_bool(name);
 			if (v != expected)
@@ -2086,20 +2086,20 @@ namespace {
 			return v;
 		}
 
-		void param_bits(Twine::Id name, int width)
+		void param_bits(TwineRef name, int width)
 		{
 			param(name);
 			if (GetSize(cell->parameters.at(name)) != width)
 				error(__LINE__);
 		}
 
-		std::string param_string(Twine::Id name)
+		std::string param_string(TwineRef name)
 		{
 			param(name);
 			return cell->parameters.at(name).decode_string();
 		}
 
-		void port(Twine::Id name, int width)
+		void port(TwineRef name, int width)
 		{
 			auto it = cell->connections_.find(name);
 			if (it == cell->connections_.end())
@@ -3016,7 +3016,7 @@ namespace {
 
 void RTLIL::Module::sort()
 {
-	auto sort_twine_by_str = [this](Twine::Id a, Twine::Id b) {
+	auto sort_twine_by_str = [this](TwineRef a, TwineRef b) {
 		return design->twines.flat_string(a) < design->twines.flat_string(b);
 	};
 	wires_.sort(sort_twine_by_str);
@@ -3075,7 +3075,7 @@ void check_module(RTLIL::Module *module, ParallelDispatchThreadPool &thread_pool
 				log_assert(!memory_strings.count(memid));
 				memids.insert(ctx, std::move(memid));
 			}
-			auto cell_mod = const_module->design->module(Twine::Id(it.second->name));
+			auto cell_mod = const_module->design->module(TwineRef(it.second->name));
 			if (cell_mod != nullptr) {
 				// assertion check below to make sure that there are no
 				// cases where a cell has a blackbox attribute since
@@ -3102,7 +3102,7 @@ void check_module(RTLIL::Module *module, ParallelDispatchThreadPool &thread_pool
 				log_assert(!it2.first.empty());
 			if (it.second->port_id) {
 				log_assert(GetSize(const_module->ports) >= it.second->port_id);
-				log_assert(const_module->ports.at(it.second->port_id-1) == Twine::Id(it.second->name));
+				log_assert(const_module->ports.at(it.second->port_id-1) == TwineRef(it.second->name));
 				log_assert(it.second->port_input || it.second->port_output);
 				log_assert(it.second->port_id <= GetSize(ports_declared));
 				bool previously_declared = ports_declared[it.second->port_id-1].set_and_return_old();
@@ -3188,7 +3188,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons
 		new_mod->attributes[attr.first] = attr.second;
 	if (src_id_verbatim) {
 		// Caller (Design::clone_into) copied twines wholesale, so
-		// Twine::Ids preserve their meaning. Allocate per-AttrObject
+		// TwineRefs preserve their meaning. Allocate per-AttrObject
 		// meta in dst's pool and copy the fields. dst's twine refcounts
 		// were inherited via the wholesale copy and already account for
 		// these new AttrObjects, so no retain on src.
@@ -3211,14 +3211,14 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons
 	}
 
 	if (src_id_verbatim) {
-		// Per-AttrObject meta clone via dst design's pool. Twine::Ids for
+		// Per-AttrObject meta clone via dst design's pool. TwineRefs for
 		// src attributes transfer verbatim (twines was wholesale-copied).
 		// name_id is re-interned by addWire/addCell; copy_meta restores it.
 		auto copy_meta = [&](const RTLIL::AttrObject *src_obj, RTLIL::AttrObject *dst_obj) {
 			if (!src_obj->meta_ || !new_mod->design)
 				return;
 			// Preserve name_id already set by addWire/addCell (in dst's pool).
-			Twine::Id saved_name_id = dst_obj->meta_ ? dst_obj->meta_->name_id : Twine::Null;
+			TwineRef saved_name_id = dst_obj->meta_ ? dst_obj->meta_->name_id : Twine::Null;
 			// Recycle old meta slot (no field releases — name_id's retain lives on).
 			if (dst_obj->meta_)
 				new_mod->design->free_obj_meta(dst_obj->meta_);
@@ -3230,7 +3230,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons
 		};
 		for (auto it = wires_.rbegin(); it != wires_.rend(); ++it) {
 			const RTLIL::Wire *o = it->second;
-			Twine::Id dst_name_id = new_mod->design->twines.copy_from(design->twines, it->first);
+			TwineRef dst_name_id = new_mod->design->twines.copy_from(design->twines, it->first);
 			RTLIL::Wire *w = new_mod->addWire(dst_name_id, o->width);
 			new_mod->design->twines.release(dst_name_id);
 			w->start_offset = o->start_offset;
@@ -3253,7 +3253,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons
 		}
 		for (auto it = cells_.rbegin(); it != cells_.rend(); ++it) {
 			const RTLIL::Cell *o = it->second;
-			Twine::Id dst_name_id = new_mod->design->twines.copy_from(design->twines, it->first);
+			TwineRef dst_name_id = new_mod->design->twines.copy_from(design->twines, it->first);
 			RTLIL::Cell *c = new_mod->addCell(dst_name_id, o->type);
 			new_mod->design->twines.release(dst_name_id);
 			c->connections_ = o->connections_;
@@ -3305,7 +3305,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons
 		// the destination design's pool. copy_from is a no-op if both
 		// designs share the same pool (same-design clone).
 		for (auto it = wires_.rbegin(); it != wires_.rend(); ++it) {
-			Twine::Id dst_id = new_mod->design->twines.copy_from(design->twines, it->first);
+			TwineRef dst_id = new_mod->design->twines.copy_from(design->twines, it->first);
 			new_mod->addWire(dst_id, it->second);
 			new_mod->design->twines.release(dst_id);
 		}
@@ -3314,7 +3314,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons
 			new_mod->addMemory(it->first, it->second);
 
 		for (auto it = cells_.rbegin(); it != cells_.rend(); ++it) {
-			Twine::Id dst_id = new_mod->design->twines.copy_from(design->twines, it->first);
+			TwineRef dst_id = new_mod->design->twines.copy_from(design->twines, it->first);
 			new_mod->addCell(dst_id, it->second);
 			new_mod->design->twines.release(dst_id);
 		}
@@ -3332,7 +3332,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons
 				// wire points to original module; look up by name in new module.
 				// Use the IdString materialisation path: works for both same-design
 				// and cross-design clones without assuming pool identity.
-				wire = mod->wire(Twine::Id(wire->name));
+				wire = mod->wire(TwineRef(wire->name));
 			});
 		}
 	};
@@ -3362,7 +3362,7 @@ RTLIL::Module *RTLIL::Module::clone(RTLIL::Design *dst, bool src_id_verbatim) co
 	return new_mod;
 }
 
-RTLIL::Module *RTLIL::Module::clone(RTLIL::Design *dst, Twine::Id target_name, bool src_id_verbatim) const
+RTLIL::Module *RTLIL::Module::clone(RTLIL::Design *dst, TwineRef target_name, bool src_id_verbatim) const
 {
 	RTLIL::Module *new_mod = new RTLIL::Module;
 	new_mod->design = dst;
@@ -3463,7 +3463,7 @@ std::vector<RTLIL::NamedObject*> RTLIL::Module::selected_members() const
 void RTLIL::Module::add(RTLIL::Wire *wire)
 {
 	log_assert(wire->meta_ && wire->meta_->name_id != Twine::Null);
-	Twine::Id id = wire->meta_->name_id;
+	TwineRef id = wire->meta_->name_id;
 	log_assert(wires_.count(id) == 0);
 	log_assert(refcount_wires_ == 0);
 	wires_[id] = wire;
@@ -3473,7 +3473,7 @@ void RTLIL::Module::add(RTLIL::Wire *wire)
 void RTLIL::Module::add(RTLIL::Cell *cell)
 {
 	log_assert(cell->meta_ && cell->meta_->name_id != Twine::Null);
-	Twine::Id id = cell->meta_->name_id;
+	TwineRef id = cell->meta_->name_id;
 	log_assert(cells_.count(id) == 0);
 	log_assert(refcount_cells_ == 0);
 	cells_[id] = cell;
@@ -3542,7 +3542,7 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
 
 	for (auto &it : wires) {
 		log_assert(it->meta_ && it->meta_->name_id != Twine::Null);
-		Twine::Id id = it->meta_->name_id;
+		TwineRef id = it->meta_->name_id;
 		log_assert(wires_.count(id) != 0);
 		wires_.erase(id);
 		delete it;  // Wire::~Wire releases src and name_id
@@ -3563,35 +3563,35 @@ void RTLIL::Module::remove(RTLIL::Process *process)
 	delete process;
 }
 
-void RTLIL::Module::rename(RTLIL::Wire *wire, Twine::Id new_name)
+void RTLIL::Module::rename(RTLIL::Wire *wire, TwineRef new_name)
 {
 	log_assert(wire->meta_ && wire->meta_->name_id != Twine::Null);
-	Twine::Id old_id = wire->meta_->name_id;
+	TwineRef old_id = wire->meta_->name_id;
 	log_assert(wires_[old_id] == wire);
 	log_assert(refcount_wires_ == 0);
 	wires_.erase(old_id);
-	Twine::Id new_id = design->twines.intern(new_name.str());
+	TwineRef new_id = design->twines.intern(new_name.str());
 	design->obj_set_name_id(wire, new_id);
 	design->twines.release(new_id);
 	add(wire);
 }
 
-void RTLIL::Module::rename(RTLIL::Cell *cell, Twine::Id new_name)
+void RTLIL::Module::rename(RTLIL::Cell *cell, TwineRef new_name)
 {
 	log_assert(cell->meta_ && cell->meta_->name_id != Twine::Null);
-	Twine::Id old_id = cell->meta_->name_id;
+	TwineRef old_id = cell->meta_->name_id;
 	log_assert(cells_[old_id] == cell);
 	log_assert(refcount_cells_ == 0);
 	cells_.erase(old_id);
-	Twine::Id new_id = design->twines.intern(new_name.str());
+	TwineRef new_id = design->twines.intern(new_name.str());
 	design->obj_set_name_id(cell, new_id);
 	design->twines.release(new_id);
 	add(cell);
 }
 
-void RTLIL::Module::rename(Twine::Id old_name, Twine::Id new_name)
+void RTLIL::Module::rename(TwineRef old_name, TwineRef new_name)
 {
-	Twine::Id old_id = design->twines.lookup(old_name.str());
+	TwineRef old_id = design->twines.lookup(old_name.str());
 	if (old_id != Twine::Null && wires_.count(old_id))
 		rename(wires_.at(old_id), new_name);
 	else if (old_id != Twine::Null && cells_.count(old_id))
@@ -3604,8 +3604,8 @@ void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
 {
 	log_assert(w1->meta_ && w1->meta_->name_id != Twine::Null);
 	log_assert(w2->meta_ && w2->meta_->name_id != Twine::Null);
-	Twine::Id id1 = w1->meta_->name_id;
-	Twine::Id id2 = w2->meta_->name_id;
+	TwineRef id1 = w1->meta_->name_id;
+	TwineRef id2 = w2->meta_->name_id;
 	log_assert(wires_[id1] == w1);
 	log_assert(wires_[id2] == w2);
 	log_assert(refcount_wires_ == 0);
@@ -3620,8 +3620,8 @@ void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
 {
 	log_assert(c1->meta_ && c1->meta_->name_id != Twine::Null);
 	log_assert(c2->meta_ && c2->meta_->name_id != Twine::Null);
-	Twine::Id id1 = c1->meta_->name_id;
-	Twine::Id id2 = c2->meta_->name_id;
+	TwineRef id1 = c1->meta_->name_id;
+	TwineRef id2 = c2->meta_->name_id;
 	log_assert(cells_[id1] == c1);
 	log_assert(cells_[id2] == c2);
 	log_assert(refcount_cells_ == 0);
@@ -3632,13 +3632,13 @@ void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
 	std::swap(c1->meta_->name_id, c2->meta_->name_id);
 }
 
-Twine::Id RTLIL::Module::uniquify(Twine::Id name)
+TwineRef RTLIL::Module::uniquify(TwineRef name)
 {
 	int index = 0;
 	return uniquify(name, index);
 }
 
-Twine::Id RTLIL::Module::uniquify(Twine::Id name, int &index)
+TwineRef RTLIL::Module::uniquify(TwineRef name, int &index)
 {
 	if (index == 0) {
 		if (count_id(name) == 0)
@@ -3647,7 +3647,7 @@ Twine::Id RTLIL::Module::uniquify(Twine::Id name, int &index)
 	}
 
 	while (1) {
-		Twine::Id new_name = stringf("%s_%d", name, index);
+		TwineRef new_name = stringf("%s_%d", name, index);
 		if (count_id(new_name) == 0)
 			return new_name;
 		index++;
@@ -3730,7 +3730,7 @@ void RTLIL::Module::fixup_ports()
 	}
 }
 
-RTLIL::Wire *RTLIL::Module::addWire(Twine::Id name, int width)
+RTLIL::Wire *RTLIL::Module::addWire(TwineRef name, int width)
 {
 	log_assert(design);
 	RTLIL::Wire *wire = new RTLIL::Wire(Wire::ConstructToken{});
@@ -3740,16 +3740,16 @@ RTLIL::Wire *RTLIL::Module::addWire(Twine::Id name, int width)
 	return wire;
 }
 
-RTLIL::Wire *RTLIL::Module::addWire(Twine::Id name, int width)
+RTLIL::Wire *RTLIL::Module::addWire(TwineRef name, int width)
 {
 	log_assert(design);
-	Twine::Id id = design->twines.intern(name.str());
+	TwineRef id = design->twines.intern(name.str());
 	RTLIL::Wire *wire = addWire(id, width);
 	design->twines.release(id);
 	return wire;
 }
 
-RTLIL::Wire *RTLIL::Module::addWire(Twine::Id name, const RTLIL::Wire *other)
+RTLIL::Wire *RTLIL::Module::addWire(TwineRef name, const RTLIL::Wire *other)
 {
 	RTLIL::Wire *wire = addWire(name);
 	wire->width = other->width;
@@ -3768,16 +3768,16 @@ RTLIL::Wire *RTLIL::Module::addWire(Twine::Id name, const RTLIL::Wire *other)
 	return wire;
 }
 
-RTLIL::Wire *RTLIL::Module::addWire(Twine::Id name, const RTLIL::Wire *other)
+RTLIL::Wire *RTLIL::Module::addWire(TwineRef name, const RTLIL::Wire *other)
 {
 	log_assert(design);
-	Twine::Id id = design->twines.intern(name.str());
+	TwineRef id = design->twines.intern(name.str());
 	RTLIL::Wire *wire = addWire(id, other);
 	design->twines.release(id);
 	return wire;
 }
 
-RTLIL::Cell *RTLIL::Module::addCell(Twine::Id name, Twine::Id type)
+RTLIL::Cell *RTLIL::Module::addCell(TwineRef name, TwineRef type)
 {
 	log_assert(design);
 	RTLIL::Cell *cell = new RTLIL::Cell(Cell::ConstructToken{});
@@ -3787,16 +3787,16 @@ RTLIL::Cell *RTLIL::Module::addCell(Twine::Id name, Twine::Id type)
 	return cell;
 }
 
-RTLIL::Cell *RTLIL::Module::addCell(Twine::Id name, Twine::Id type)
+RTLIL::Cell *RTLIL::Module::addCell(TwineRef name, TwineRef type)
 {
 	log_assert(design);
-	Twine::Id id = design->twines.intern(name.str());
+	TwineRef id = design->twines.intern(name.str());
 	RTLIL::Cell *cell = addCell(id, type);
 	design->twines.release(id);
 	return cell;
 }
 
-RTLIL::Cell *RTLIL::Module::addCell(Twine::Id name, const RTLIL::Cell *other)
+RTLIL::Cell *RTLIL::Module::addCell(TwineRef name, const RTLIL::Cell *other)
 {
 	RTLIL::Cell *cell = addCell(name, other->type);
 	cell->connections_ = other->connections_;
@@ -3810,16 +3810,16 @@ RTLIL::Cell *RTLIL::Module::addCell(Twine::Id name, const RTLIL::Cell *other)
 	return cell;
 }
 
-RTLIL::Cell *RTLIL::Module::addCell(Twine::Id name, const RTLIL::Cell *other)
+RTLIL::Cell *RTLIL::Module::addCell(TwineRef name, const RTLIL::Cell *other)
 {
 	log_assert(design);
-	Twine::Id id = design->twines.intern(name.str());
+	TwineRef id = design->twines.intern(name.str());
 	RTLIL::Cell *cell = addCell(id, other);
 	design->twines.release(id);
 	return cell;
 }
 
-RTLIL::Memory *RTLIL::Module::addMemory(Twine::Id name)
+RTLIL::Memory *RTLIL::Module::addMemory(TwineRef name)
 {
 	RTLIL::Memory *mem = new RTLIL::Memory;
 	mem->name = std::move(name);
@@ -3828,7 +3828,7 @@ RTLIL::Memory *RTLIL::Module::addMemory(Twine::Id name)
 	return mem;
 }
 
-RTLIL::Memory *RTLIL::Module::addMemory(Twine::Id name, const RTLIL::Memory *other)
+RTLIL::Memory *RTLIL::Module::addMemory(TwineRef name, const RTLIL::Memory *other)
 {
 	RTLIL::Memory *mem = new RTLIL::Memory;
 	mem->name = std::move(name);
@@ -3847,7 +3847,7 @@ RTLIL::Memory *RTLIL::Module::addMemory(Twine::Id name, const RTLIL::Memory *oth
 	return mem;
 }
 
-RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name)
+RTLIL::Process *RTLIL::Module::addProcess(TwineRef name)
 {
 	RTLIL::Process *proc = new RTLIL::Process;
 	proc->name = std::move(name);
@@ -3896,7 +3896,7 @@ namespace {
 	}
 }
 
-RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *other)
+RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *other)
 {
 	RTLIL::Process *proc = other->clone();
 	proc->name = std::move(name);
@@ -3918,7 +3918,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 }
 
 	#define DEF_METHOD(_func, _y_size, _type) \
-		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const RTLIL::SrcAttr &src) { \
 			RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, _type);           \
 			cell->parameters[ID::A_SIGNED] = is_signed;         \
 			cell->parameters[ID::A_WIDTH] = sig_a.size();       \
@@ -3928,7 +3928,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 			cell->set_src_attribute(src);                       \
 			return cell;                                        \
 		} \
-		template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine::Id name, const RTLIL::SigSpec &sig_a, bool is_signed, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(TwineRef name, const RTLIL::SigSpec &sig_a, bool is_signed, const RTLIL::SrcAttr &src) { \
 			RTLIL::SigSpec sig_y = static_cast<Derived*>(this)->addWire(NEW_ID, _y_size);    \
 			add ## _func(name, sig_a, sig_y, is_signed, src);   \
 			return sig_y;                                       \
@@ -3945,7 +3945,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 	#undef DEF_METHOD
 
 	#define DEF_METHOD(_func, _y_size, _type) \
-		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool /* is_signed */, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool /* is_signed */, const RTLIL::SrcAttr &src) { \
 			RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, _type);           \
 			cell->parameters[ID::WIDTH] = sig_a.size();         \
 			cell->setPort(ID::A, sig_a);                        \
@@ -3953,7 +3953,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 			cell->set_src_attribute(src);                       \
 			return cell;                                        \
 		} \
-		template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine::Id name, const RTLIL::SigSpec &sig_a, bool is_signed, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(TwineRef name, const RTLIL::SigSpec &sig_a, bool is_signed, const RTLIL::SrcAttr &src) { \
 			RTLIL::SigSpec sig_y = static_cast<Derived*>(this)->addWire(NEW_ID, _y_size);    \
 			add ## _func(name, sig_a, sig_y, is_signed, src);   \
 			return sig_y;                                       \
@@ -3962,7 +3962,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 	#undef DEF_METHOD
 
 	#define DEF_METHOD(_func, _y_size, _type) \
-		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const RTLIL::SrcAttr &src) { \
 			RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, _type);           \
 			cell->parameters[ID::A_SIGNED] = is_signed;         \
 			cell->parameters[ID::B_SIGNED] = is_signed;         \
@@ -3975,7 +3975,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 			cell->set_src_attribute(src);                       \
 			return cell;                                        \
 		} \
-		template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const RTLIL::SrcAttr &src) { \
 			RTLIL::SigSpec sig_y = static_cast<Derived*>(this)->addWire(NEW_ID, _y_size);         \
 			add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
 			return sig_y;                                            \
@@ -4005,7 +4005,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 	#undef DEF_METHOD
 
 	#define DEF_METHOD(_func, _y_size, _type) \
-		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const RTLIL::SrcAttr &src) { \
 			RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, _type);           \
 			cell->parameters[ID::A_SIGNED] = is_signed;         \
 			cell->parameters[ID::B_SIGNED] = false;             \
@@ -4018,7 +4018,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 			cell->set_src_attribute(src);                       \
 			return cell;                                        \
 		} \
-		template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const RTLIL::SrcAttr &src) { \
 			RTLIL::SigSpec sig_y = static_cast<Derived*>(this)->addWire(NEW_ID, _y_size);         \
 			add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
 			return sig_y;                                            \
@@ -4030,7 +4030,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 	#undef DEF_METHOD
 
 	#define DEF_METHOD(_func, _y_size, _type) \
-		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const RTLIL::SrcAttr &src) { \
 			RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, _type);           \
 			cell->parameters[ID::A_SIGNED] = false;             \
 			cell->parameters[ID::B_SIGNED] = is_signed;         \
@@ -4043,7 +4043,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 			cell->set_src_attribute(src);                       \
 			return cell;                                        \
 		} \
-		template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const RTLIL::SrcAttr &src) { \
 			RTLIL::SigSpec sig_y = static_cast<Derived*>(this)->addWire(NEW_ID, _y_size);         \
 			add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
 			return sig_y;                                            \
@@ -4052,7 +4052,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 	#undef DEF_METHOD
 
 	#define DEF_METHOD(_func, _type, _pmux) \
-		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src) { \
 			RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, _type);                 \
 			cell->parameters[ID::WIDTH] = sig_a.size();               \
 			if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size();  \
@@ -4063,7 +4063,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 			cell->set_src_attribute(src);                             \
 			return cell;                                              \
 		} \
-		template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SrcAttr &src) { \
 			RTLIL::SigSpec sig_y = static_cast<Derived*>(this)->addWire(NEW_ID, sig_a.size());     \
 			add ## _func(name, sig_a, sig_b, sig_s, sig_y, src);      \
 			return sig_y;                                             \
@@ -4074,7 +4074,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 	#undef DEF_METHOD
 
 	#define DEF_METHOD(_func, _type, _demux) \
-		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src) { \
 			RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, _type);                 \
 			cell->parameters[ID::WIDTH] = _demux ? sig_a.size() : sig_y.size(); \
 			cell->parameters[ID::S_WIDTH] = sig_s.size();             \
@@ -4084,7 +4084,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 			cell->set_src_attribute(src);                             \
 			return cell;                                              \
 		} \
-		template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SrcAttr &src) { \
 			RTLIL::SigSpec sig_y = static_cast<Derived*>(this)->addWire(NEW_ID, _demux ? sig_a.size() << sig_s.size() : sig_a.size() >> sig_s.size()); \
 			add ## _func(name, sig_a, sig_s, sig_y, src);             \
 			return sig_y;                                             \
@@ -4094,7 +4094,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 	#undef DEF_METHOD
 
 	#define DEF_METHOD(_func, _type) \
-		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src) { \
 			RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, _type);                 \
 			cell->parameters[ID::WIDTH] = sig_a.size();               \
 			cell->setPort(ID::A, sig_a);                              \
@@ -4103,7 +4103,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 			cell->set_src_attribute(src);                             \
 			return cell;                                              \
 		} \
-		template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SrcAttr &src) { \
 			RTLIL::SigSpec sig_y = static_cast<Derived*>(this)->addWire(NEW_ID, sig_a.size());     \
 			add ## _func(name, sig_a, sig_s, sig_y, src);             \
 			return sig_y;                                             \
@@ -4112,20 +4112,20 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 	#undef DEF_METHOD
 
 	#define DEF_METHOD_2(_func, _type, _P1, _P2) \
-		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(Twine::Id name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(TwineRef name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SrcAttr &src) { \
 			RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, _type);         \
 			cell->setPort("\\" #_P1, sig1);                   \
 			cell->setPort("\\" #_P2, sig2);                   \
 			cell->set_src_attribute(src);                     \
 			return cell;                                      \
 		} \
-		template<typename Derived> RTLIL::SigBit CellAdderMixin<Derived>::_func(Twine::Id name, const RTLIL::SigBit &sig1, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::SigBit CellAdderMixin<Derived>::_func(TwineRef name, const RTLIL::SigBit &sig1, const RTLIL::SrcAttr &src) { \
 			RTLIL::SigBit sig2 = static_cast<Derived*>(this)->addWire(NEW_ID);             \
 			add ## _func(name, sig1, sig2, src);              \
 			return sig2;                                      \
 		}
 	#define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
-		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(Twine::Id name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(TwineRef name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SrcAttr &src) { \
 			RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, _type);         \
 			cell->setPort("\\" #_P1, sig1);                   \
 			cell->setPort("\\" #_P2, sig2);                   \
@@ -4133,13 +4133,13 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 			cell->set_src_attribute(src);                     \
 			return cell;                                      \
 		} \
-		template<typename Derived> RTLIL::SigBit CellAdderMixin<Derived>::_func(Twine::Id name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::SigBit CellAdderMixin<Derived>::_func(TwineRef name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SrcAttr &src) { \
 			RTLIL::SigBit sig3 = static_cast<Derived*>(this)->addWire(NEW_ID);             \
 			add ## _func(name, sig1, sig2, sig3, src);        \
 			return sig3;                                      \
 		}
 	#define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
-		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(Twine::Id name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(TwineRef name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SrcAttr &src) { \
 			RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, _type);         \
 			cell->setPort("\\" #_P1, sig1);                   \
 			cell->setPort("\\" #_P2, sig2);                   \
@@ -4148,13 +4148,13 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 			cell->set_src_attribute(src);                     \
 			return cell;                                      \
 		} \
-		template<typename Derived> RTLIL::SigBit CellAdderMixin<Derived>::_func(Twine::Id name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::SigBit CellAdderMixin<Derived>::_func(TwineRef name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SrcAttr &src) { \
 			RTLIL::SigBit sig4 = static_cast<Derived*>(this)->addWire(NEW_ID);             \
 			add ## _func(name, sig1, sig2, sig3, sig4, src);  \
 			return sig4;                                      \
 		}
 	#define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
-		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(Twine::Id name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::add ## _func(TwineRef name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const RTLIL::SrcAttr &src) { \
 			RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, _type);         \
 			cell->setPort("\\" #_P1, sig1);                   \
 			cell->setPort("\\" #_P2, sig2);                   \
@@ -4164,7 +4164,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 			cell->set_src_attribute(src);                     \
 			return cell;                                      \
 		} \
-		template<typename Derived> RTLIL::SigBit CellAdderMixin<Derived>::_func(Twine::Id name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SrcAttr &src) { \
+		template<typename Derived> RTLIL::SigBit CellAdderMixin<Derived>::_func(TwineRef name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SrcAttr &src) { \
 			RTLIL::SigBit sig5 = static_cast<Derived*>(this)->addWire(NEW_ID);                  \
 			add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
 			return sig5;                                           \
@@ -4190,7 +4190,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 	#undef DEF_METHOD_4
 	#undef DEF_METHOD_5
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addPow(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addPow(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($pow));
 		cell->parameters[ID::A_SIGNED] = a_signed;
@@ -4205,7 +4205,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addFa(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addFa(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($fa));
 		cell->parameters[ID::WIDTH] = sig_a.size();
@@ -4218,7 +4218,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSlice(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSlice(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($slice));
 		cell->parameters[ID::A_WIDTH] = sig_a.size();
@@ -4230,7 +4230,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addConcat(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addConcat(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($concat));
 		cell->parameters[ID::A_WIDTH] = sig_a.size();
@@ -4242,7 +4242,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addLut(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addLut(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($lut));
 		cell->parameters[ID::LUT] = lut;
@@ -4253,7 +4253,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addTribuf(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addTribuf(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($tribuf));
 		cell->parameters[ID::WIDTH] = sig_a.size();
@@ -4264,7 +4264,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAssert(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAssert(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($assert));
 		cell->setPort(ID::A, sig_a);
@@ -4273,7 +4273,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAssume(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAssume(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($assume));
 		cell->setPort(ID::A, sig_a);
@@ -4282,7 +4282,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addLive(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addLive(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($live));
 		cell->setPort(ID::A, sig_a);
@@ -4291,7 +4291,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addFair(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addFair(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($fair));
 		cell->setPort(ID::A, sig_a);
@@ -4300,7 +4300,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addCover(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addCover(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($cover));
 		cell->setPort(ID::A, sig_a);
@@ -4309,7 +4309,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addEquiv(Twine::Id name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addEquiv(TwineRef name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($equiv));
 		cell->setPort(ID::A, sig_a);
@@ -4319,7 +4319,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSr(Twine::Id name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSr(TwineRef name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($sr));
 		cell->parameters[ID::SET_POLARITY] = set_polarity;
@@ -4332,7 +4332,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addFf(Twine::Id name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addFf(TwineRef name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($ff));
 		cell->parameters[ID::WIDTH] = sig_q.size();
@@ -4342,7 +4342,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDff(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDff(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($dff));
 		cell->parameters[ID::CLK_POLARITY] = clk_polarity;
@@ -4354,7 +4354,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffe(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffe(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($dffe));
 		cell->parameters[ID::CLK_POLARITY] = clk_polarity;
@@ -4368,7 +4368,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffsr(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffsr(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
 			RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($dffsr));
@@ -4385,7 +4385,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffsre(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffsre(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
 			RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($dffsre));
@@ -4404,7 +4404,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAdff(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAdff(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($adff));
@@ -4420,7 +4420,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAdffe(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAdffe(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			RTLIL::Const arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($adffe));
@@ -4438,7 +4438,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAldff(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAldff(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool aload_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($aldff));
@@ -4454,7 +4454,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAldffe(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAldffe(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool en_polarity, bool aload_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($aldffe));
@@ -4472,7 +4472,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSdff(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSdff(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			RTLIL::Const srst_value, bool clk_polarity, bool srst_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($sdff));
@@ -4488,7 +4488,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSdffe(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSdffe(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($sdffe));
@@ -4506,7 +4506,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSdffce(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSdffce(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($sdffce));
@@ -4524,7 +4524,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDlatch(Twine::Id name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDlatch(TwineRef name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($dlatch));
 		cell->parameters[ID::EN_POLARITY] = en_polarity;
@@ -4536,7 +4536,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAdlatch(Twine::Id name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAdlatch(TwineRef name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			RTLIL::Const arst_value, bool en_polarity, bool arst_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($adlatch));
@@ -4552,7 +4552,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDlatchsr(Twine::Id name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDlatchsr(TwineRef name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
 			RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($dlatchsr));
@@ -4569,7 +4569,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSrGate(Twine::Id name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSrGate(TwineRef name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
 			const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, stringf("$_SR_%c%c_", set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
@@ -4580,7 +4580,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addFfGate(Twine::Id name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addFfGate(TwineRef name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, ID($_FF_));
 		cell->setPort(ID::D, sig_d);
@@ -4589,7 +4589,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffGate(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
 		cell->setPort(ID::C, sig_clk);
@@ -4599,7 +4599,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffeGate(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffeGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
 		cell->setPort(ID::C, sig_clk);
@@ -4610,7 +4610,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffsrGate(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffsrGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
 			RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
@@ -4623,7 +4623,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffsreGate(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDffsreGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
 			RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, stringf("$_DFFSRE_%c%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
@@ -4637,7 +4637,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAdffGate(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAdffGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			bool arst_value, bool clk_polarity, bool arst_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
@@ -4649,7 +4649,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAdffeGate(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAdffeGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			bool arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, stringf("$_DFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
@@ -4662,7 +4662,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAldffGate(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAldffGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool aload_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, stringf("$_ALDFF_%c%c_", clk_polarity ? 'P' : 'N', aload_polarity ? 'P' : 'N'));
@@ -4675,7 +4675,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAldffeGate(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAldffeGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool en_polarity, bool aload_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, stringf("$_ALDFFE_%c%c%c_", clk_polarity ? 'P' : 'N', aload_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
@@ -4689,7 +4689,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSdffGate(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSdffGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			bool srst_value, bool clk_polarity, bool srst_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, stringf("$_SDFF_%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0'));
@@ -4701,7 +4701,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSdffeGate(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSdffeGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, stringf("$_SDFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
@@ -4714,7 +4714,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSdffceGate(Twine::Id name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addSdffceGate(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, stringf("$_SDFFCE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
@@ -4727,7 +4727,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDlatchGate(Twine::Id name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const RTLIL::SrcAttr &src)
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDlatchGate(TwineRef name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
 		cell->setPort(ID::E, sig_en);
@@ -4737,7 +4737,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAdlatchGate(Twine::Id name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addAdlatchGate(TwineRef name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
 			bool arst_value, bool en_polarity, bool arst_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, stringf("$_DLATCH_%c%c%c_", en_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
@@ -4749,7 +4749,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDlatchsrGate(Twine::Id name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
+	template<typename Derived> RTLIL::Cell* CellAdderMixin<Derived>::addDlatchsrGate(TwineRef name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
 			RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const RTLIL::SrcAttr &src)
 	{
 		RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
@@ -4762,7 +4762,7 @@ RTLIL::Process *RTLIL::Module::addProcess(Twine::Id name, const RTLIL::Process *
 		return cell;
 	}
 
-RTLIL::Cell* RTLIL::Module::addAnyinit(Twine::Id name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SrcAttr &src)
+RTLIL::Cell* RTLIL::Module::addAnyinit(TwineRef name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SrcAttr &src)
 {
 	RTLIL::Cell *cell = addCell(name, ID($anyinit));
 	cell->parameters[ID::WIDTH] = sig_q.size();
@@ -4772,7 +4772,7 @@ RTLIL::Cell* RTLIL::Module::addAnyinit(Twine::Id name, const RTLIL::SigSpec &sig
 	return cell;
 }
 
-RTLIL::SigSpec RTLIL::Module::Anyconst(Twine::Id name, int width, const RTLIL::SrcAttr &src)
+RTLIL::SigSpec RTLIL::Module::Anyconst(TwineRef name, int width, const RTLIL::SrcAttr &src)
 {
 	RTLIL::SigSpec sig = addWire(NEW_ID, width);
 	Cell *cell = addCell(name, ID($anyconst));
@@ -4782,7 +4782,7 @@ RTLIL::SigSpec RTLIL::Module::Anyconst(Twine::Id name, int width, const RTLIL::S
 	return sig;
 }
 
-RTLIL::SigSpec RTLIL::Module::Anyseq(Twine::Id name, int width, const RTLIL::SrcAttr &src)
+RTLIL::SigSpec RTLIL::Module::Anyseq(TwineRef name, int width, const RTLIL::SrcAttr &src)
 {
 	RTLIL::SigSpec sig = addWire(NEW_ID, width);
 	Cell *cell = addCell(name, ID($anyseq));
@@ -4792,7 +4792,7 @@ RTLIL::SigSpec RTLIL::Module::Anyseq(Twine::Id name, int width, const RTLIL::Src
 	return sig;
 }
 
-RTLIL::SigSpec RTLIL::Module::Allconst(Twine::Id name, int width, const RTLIL::SrcAttr &src)
+RTLIL::SigSpec RTLIL::Module::Allconst(TwineRef name, int width, const RTLIL::SrcAttr &src)
 {
 	RTLIL::SigSpec sig = addWire(NEW_ID, width);
 	Cell *cell = addCell(name, ID($allconst));
@@ -4802,7 +4802,7 @@ RTLIL::SigSpec RTLIL::Module::Allconst(Twine::Id name, int width, const RTLIL::S
 	return sig;
 }
 
-RTLIL::SigSpec RTLIL::Module::Allseq(Twine::Id name, int width, const RTLIL::SrcAttr &src)
+RTLIL::SigSpec RTLIL::Module::Allseq(TwineRef name, int width, const RTLIL::SrcAttr &src)
 {
 	RTLIL::SigSpec sig = addWire(NEW_ID, width);
 	Cell *cell = addCell(name, ID($allseq));
@@ -4812,7 +4812,7 @@ RTLIL::SigSpec RTLIL::Module::Allseq(Twine::Id name, int width, const RTLIL::Src
 	return sig;
 }
 
-RTLIL::SigSpec RTLIL::Module::Initstate(Twine::Id name, const RTLIL::SrcAttr &src)
+RTLIL::SigSpec RTLIL::Module::Initstate(TwineRef name, const RTLIL::SrcAttr &src)
 {
 	RTLIL::SigSpec sig = addWire(NEW_ID);
 	Cell *cell = addCell(name, ID($initstate));
@@ -4821,7 +4821,7 @@ RTLIL::SigSpec RTLIL::Module::Initstate(Twine::Id name, const RTLIL::SrcAttr &sr
 	return sig;
 }
 
-RTLIL::SigSpec RTLIL::Module::SetTag(Twine::Id name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SrcAttr &src)
+RTLIL::SigSpec RTLIL::Module::SetTag(TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SrcAttr &src)
 {
 	RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size());
 	Cell *cell = addCell(name, ID($set_tag));
@@ -4835,7 +4835,7 @@ RTLIL::SigSpec RTLIL::Module::SetTag(Twine::Id name, const std::string &tag, con
 	return sig;
 }
 
-RTLIL::Cell* RTLIL::Module::addSetTag(Twine::Id name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src)
+RTLIL::Cell* RTLIL::Module::addSetTag(TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src)
 {
 	Cell *cell = addCell(name, ID($set_tag));
 	cell->parameters[ID::WIDTH] = sig_a.size();
@@ -4848,7 +4848,7 @@ RTLIL::Cell* RTLIL::Module::addSetTag(Twine::Id name, const std::string &tag, co
 	return cell;
 }
 
-RTLIL::SigSpec RTLIL::Module::GetTag(Twine::Id name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SrcAttr &src)
+RTLIL::SigSpec RTLIL::Module::GetTag(TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SrcAttr &src)
 {
 	RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size());
 	Cell *cell = addCell(name, ID($get_tag));
@@ -4860,7 +4860,7 @@ RTLIL::SigSpec RTLIL::Module::GetTag(Twine::Id name, const std::string &tag, con
 	return sig;
 }
 
-RTLIL::Cell* RTLIL::Module::addOverwriteTag(Twine::Id name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SrcAttr &src)
+RTLIL::Cell* RTLIL::Module::addOverwriteTag(TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SrcAttr &src)
 {
 	RTLIL::Cell *cell = addCell(name, ID($overwrite_tag));
 	cell->parameters[ID::WIDTH] = sig_a.size();
@@ -4872,7 +4872,7 @@ RTLIL::Cell* RTLIL::Module::addOverwriteTag(Twine::Id name, const std::string &t
 	return cell;
 }
 
-RTLIL::SigSpec RTLIL::Module::OriginalTag(Twine::Id name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SrcAttr &src)
+RTLIL::SigSpec RTLIL::Module::OriginalTag(TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SrcAttr &src)
 {
 	RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size());
 	Cell *cell = addCell(name, ID($original_tag));
@@ -4884,7 +4884,7 @@ RTLIL::SigSpec RTLIL::Module::OriginalTag(Twine::Id name, const std::string &tag
 	return sig;
 }
 
-RTLIL::SigSpec RTLIL::Module::FutureFF(Twine::Id name, const RTLIL::SigSpec &sig_e, const RTLIL::SrcAttr &src)
+RTLIL::SigSpec RTLIL::Module::FutureFF(TwineRef name, const RTLIL::SigSpec &sig_e, const RTLIL::SrcAttr &src)
 {
 	RTLIL::SigSpec sig = addWire(NEW_ID, sig_e.size());
 	Cell *cell = addCell(name, ID($future_ff));
@@ -4933,14 +4933,14 @@ RTLIL::Wire::~Wire()
 #endif
 }
 
-Twine::Id RTLIL::Wire::src_id() const
+TwineRef RTLIL::Wire::src_id() const
 {
 	if (!module || !module->design)
 		return Twine::Null;
 	return module->design->obj_src_id(this);
 }
 
-void RTLIL::Wire::set_src_id(Twine::Id id)
+void RTLIL::Wire::set_src_id(TwineRef id)
 {
 	log_assert(module && module->design && "Wire::set_src_id requires the wire to be attached to a module in a design");
 	module->design->obj_set_src_id(this, id);
@@ -4967,7 +4967,7 @@ void RTLIL::Wire::adopt_src_from(const RTLIL::AttrObject *source)
 	module->design->adopt_src_from(this, source);
 }
 
-void RTLIL::Wire::absorb_attrs(dict<Twine::Id, RTLIL::Const> &&buf)
+void RTLIL::Wire::absorb_attrs(dict<TwineRef, RTLIL::Const> &&buf)
 {
 	log_assert(module && module->design && "Wire::absorb_attrs requires the wire to be attached to a module in a design");
 	module->design->absorb_attrs(this, std::move(buf));
@@ -5048,23 +5048,21 @@ RTLIL::Cell::~Cell()
 #endif
 }
 
-Twine::Id RTLIL::Cell::src_id() const
+TwineRef RTLIL::Cell::src_id() const
 {
 	if (!module || !module->design)
 		return Twine::Null;
 	return module->design->obj_src_id(this);
 }
 
-void RTLIL::Cell::set_src_id(Twine::Id id)
+void RTLIL::Cell::set_src_id(TwineRef id)
 {
 	log_assert(module && module->design && "Cell::set_src_id requires the cell to be attached to a module in a design");
 	module->design->obj_set_src_id(this, id);
 }
 
-void RTLIL::Cell::set_src_attribute(const RTLIL::SrcAttr &src)
+void RTLIL::Cell::set_src_attribute(RTLIL::SrcAttr src)
 {
-	if (src.empty() && meta_ == nullptr)
-		return;
 	log_assert(module && module->design && "Cell::set_src_attribute requires the cell to be attached to a module in a design");
 	module->design->set_src_attribute(this, src);
 }
@@ -5082,7 +5080,7 @@ void RTLIL::Cell::adopt_src_from(const RTLIL::AttrObject *source)
 	module->design->adopt_src_from(this, source);
 }
 
-void RTLIL::Cell::absorb_attrs(dict<Twine::Id, RTLIL::Const> &&buf)
+void RTLIL::Cell::absorb_attrs(dict<TwineRef, RTLIL::Const> &&buf)
 {
 	log_assert(module && module->design && "Cell::absorb_attrs requires the cell to be attached to a module in a design");
 	module->design->absorb_attrs(this, std::move(buf));
@@ -5103,19 +5101,19 @@ std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
 }
 #endif
 
-bool RTLIL::Cell::hasPort(Twine::Id portname) const
+bool RTLIL::Cell::hasPort(TwineRef portname) const
 {
 	return connections_.count(portname) != 0;
 }
 
 // bufnorm
 
-const RTLIL::SigSpec &RTLIL::Cell::getPort(Twine::Id portname) const
+const RTLIL::SigSpec &RTLIL::Cell::getPort(TwineRef portname) const
 {
 	return connections_.at(portname);
 }
 
-const dict<Twine::Id, RTLIL::SigSpec> &RTLIL::Cell::connections() const
+const dict<TwineRef, RTLIL::SigSpec> &RTLIL::Cell::connections() const
 {
 	return connections_;
 }
@@ -5129,7 +5127,7 @@ bool RTLIL::Cell::known() const
 	return false;
 }
 
-bool RTLIL::Cell::input(Twine::Id portname) const
+bool RTLIL::Cell::input(TwineRef portname) const
 {
 	if (yosys_celltypes.cell_known(type))
 		return yosys_celltypes.cell_input(type, portname);
@@ -5141,7 +5139,7 @@ bool RTLIL::Cell::input(Twine::Id portname) const
 	return false;
 }
 
-bool RTLIL::Cell::output(Twine::Id portname) const
+bool RTLIL::Cell::output(TwineRef portname) const
 {
 	if (yosys_celltypes.cell_known(type))
 		return yosys_celltypes.cell_output(type, portname);
@@ -5153,7 +5151,7 @@ bool RTLIL::Cell::output(Twine::Id portname) const
 	return false;
 }
 
-RTLIL::PortDir RTLIL::Cell::port_dir(Twine::Id portname) const
+RTLIL::PortDir RTLIL::Cell::port_dir(TwineRef portname) const
 {
 	if (yosys_celltypes.cell_known(type))
 		return yosys_celltypes.cell_port_dir(type, portname);
@@ -5169,22 +5167,22 @@ RTLIL::PortDir RTLIL::Cell::port_dir(Twine::Id portname) const
 	return PortDir::PD_UNKNOWN;
 }
 
-bool RTLIL::Cell::hasParam(Twine::Id paramname) const
+bool RTLIL::Cell::hasParam(TwineRef paramname) const
 {
 	return parameters.count(paramname) != 0;
 }
 
-void RTLIL::Cell::unsetParam(Twine::Id paramname)
+void RTLIL::Cell::unsetParam(TwineRef paramname)
 {
 	parameters.erase(paramname);
 }
 
-void RTLIL::Cell::setParam(Twine::Id paramname, RTLIL::Const value)
+void RTLIL::Cell::setParam(TwineRef paramname, RTLIL::Const value)
 {
 	parameters[paramname] = std::move(value);
 }
 
-const RTLIL::Const &RTLIL::Cell::getParam(Twine::Id paramname) const
+const RTLIL::Const &RTLIL::Cell::getParam(TwineRef paramname) const
 {
 	const auto &it = parameters.find(paramname);
 	if (it != parameters.end())
@@ -6593,12 +6591,12 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
 		}
 
 		{
-			Twine::Id wid = module->design->twines.lookup(netname);
+			TwineRef wid = module->design->twines.lookup(netname);
 			if (wid == Twine::Null || module->wires_.count(wid) == 0)
 				return false;
 		}
 
-		RTLIL::Wire *wire = module->wire(Twine::Id(netname));
+		RTLIL::Wire *wire = module->wire(TwineRef(netname));
 		if (!indices.empty()) {
 			std::vector<std::string> index_tokens;
 			sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
@@ -6639,7 +6637,7 @@ bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL
 	sig = RTLIL::SigSpec();
 	RTLIL::Selection &sel = design->selection_vars.at(str);
 	for (auto &it : module->wires_)
-		if (sel.selected_member(module->name, Twine::Id(it.second->name)))
+		if (sel.selected_member(module->name, TwineRef(it.second->name)))
 			sig.append(it.second);
 
 	return true;
@@ -6795,14 +6793,14 @@ RTLIL::Process::~Process()
 		delete *it;
 }
 
-Twine::Id RTLIL::Process::src_id() const
+TwineRef RTLIL::Process::src_id() const
 {
 	if (!module || !module->design)
 		return Twine::Null;
 	return module->design->obj_src_id(this);
 }
 
-void RTLIL::Process::set_src_id(Twine::Id id)
+void RTLIL::Process::set_src_id(TwineRef id)
 {
 	log_assert(module && module->design && "Process::set_src_id requires the process to be attached to a module in a design");
 	module->design->obj_set_src_id(this, id);
@@ -6829,7 +6827,7 @@ void RTLIL::Process::adopt_src_from(const RTLIL::AttrObject *source)
 	module->design->adopt_src_from(this, source);
 }
 
-void RTLIL::Process::absorb_attrs(dict<Twine::Id, RTLIL::Const> &&buf)
+void RTLIL::Process::absorb_attrs(dict<TwineRef, RTLIL::Const> &&buf)
 {
 	log_assert(module && module->design && "Process::absorb_attrs requires the process to be attached to a module in a design");
 	module->design->absorb_attrs(this, std::move(buf));
@@ -6864,14 +6862,14 @@ RTLIL::Memory::~Memory()
 #endif
 }
 
-Twine::Id RTLIL::Memory::src_id() const
+TwineRef RTLIL::Memory::src_id() const
 {
 	if (!module || !module->design)
 		return Twine::Null;
 	return module->design->obj_src_id(this);
 }
 
-void RTLIL::Memory::set_src_id(Twine::Id id)
+void RTLIL::Memory::set_src_id(TwineRef id)
 {
 	log_assert(module && module->design && "Memory::set_src_id requires the memory to be attached to a module in a design");
 	module->design->obj_set_src_id(this, id);
@@ -6898,7 +6896,7 @@ void RTLIL::Memory::adopt_src_from(const RTLIL::AttrObject *source)
 	module->design->adopt_src_from(this, source);
 }
 
-void RTLIL::Memory::absorb_attrs(dict<Twine::Id, RTLIL::Const> &&buf)
+void RTLIL::Memory::absorb_attrs(dict<TwineRef, RTLIL::Const> &&buf)
 {
 	log_assert(module && module->design && "Memory::absorb_attrs requires the memory to be attached to a module in a design");
 	module->design->absorb_attrs(this, std::move(buf));
@@ -6906,13 +6904,13 @@ void RTLIL::Memory::absorb_attrs(dict<Twine::Id, RTLIL::Const> &&buf)
 
 // CaseRule / SwitchRule / MemWriteAction src helpers — all delegate to
 // module->design->obj_* via the back-pointer added in the earlier commit.
-Twine::Id RTLIL::CaseRule::src_id() const
+TwineRef RTLIL::CaseRule::src_id() const
 {
 	if (!module || !module->design)
 		return Twine::Null;
 	return module->design->obj_src_id(this);
 }
-void RTLIL::CaseRule::set_src_id(Twine::Id id)
+void RTLIL::CaseRule::set_src_id(TwineRef id)
 {
 	log_assert(module && module->design && "CaseRule::set_src_id requires the case to belong to a module in a design");
 	module->design->obj_set_src_id(this, id);
@@ -6935,19 +6933,19 @@ void RTLIL::CaseRule::adopt_src_from(const RTLIL::AttrObject *source)
 	log_assert(module && module->design && "CaseRule::adopt_src_from requires the case to belong to a module in a design");
 	module->design->adopt_src_from(this, source);
 }
-void RTLIL::CaseRule::absorb_attrs(dict<Twine::Id, RTLIL::Const> &&buf)
+void RTLIL::CaseRule::absorb_attrs(dict<TwineRef, RTLIL::Const> &&buf)
 {
 	log_assert(module && module->design && "CaseRule::absorb_attrs requires the case to belong to a module in a design");
 	module->design->absorb_attrs(this, std::move(buf));
 }
 
-Twine::Id RTLIL::SwitchRule::src_id() const
+TwineRef RTLIL::SwitchRule::src_id() const
 {
 	if (!module || !module->design)
 		return Twine::Null;
 	return module->design->obj_src_id(this);
 }
-void RTLIL::SwitchRule::set_src_id(Twine::Id id)
+void RTLIL::SwitchRule::set_src_id(TwineRef id)
 {
 	log_assert(module && module->design && "SwitchRule::set_src_id requires the switch to belong to a module in a design");
 	module->design->obj_set_src_id(this, id);
@@ -6970,19 +6968,19 @@ void RTLIL::SwitchRule::adopt_src_from(const RTLIL::AttrObject *source)
 	log_assert(module && module->design && "SwitchRule::adopt_src_from requires the switch to belong to a module in a design");
 	module->design->adopt_src_from(this, source);
 }
-void RTLIL::SwitchRule::absorb_attrs(dict<Twine::Id, RTLIL::Const> &&buf)
+void RTLIL::SwitchRule::absorb_attrs(dict<TwineRef, RTLIL::Const> &&buf)
 {
 	log_assert(module && module->design && "SwitchRule::absorb_attrs requires the switch to belong to a module in a design");
 	module->design->absorb_attrs(this, std::move(buf));
 }
 
-Twine::Id RTLIL::MemWriteAction::src_id() const
+TwineRef RTLIL::MemWriteAction::src_id() const
 {
 	if (!module || !module->design)
 		return Twine::Null;
 	return module->design->obj_src_id(this);
 }
-void RTLIL::MemWriteAction::set_src_id(Twine::Id id)
+void RTLIL::MemWriteAction::set_src_id(TwineRef id)
 {
 	log_assert(module && module->design && "MemWriteAction::set_src_id requires the action to belong to a module in a design");
 	module->design->obj_set_src_id(this, id);
@@ -7005,7 +7003,7 @@ void RTLIL::MemWriteAction::adopt_src_from(const RTLIL::AttrObject *source)
 	log_assert(module && module->design && "MemWriteAction::adopt_src_from requires the action to belong to a module in a design");
 	module->design->adopt_src_from(this, source);
 }
-void RTLIL::MemWriteAction::absorb_attrs(dict<Twine::Id, RTLIL::Const> &&buf)
+void RTLIL::MemWriteAction::absorb_attrs(dict<TwineRef, RTLIL::Const> &&buf)
 {
 	log_assert(module && module->design && "MemWriteAction::absorb_attrs requires the action to belong to a module in a design");
 	module->design->absorb_attrs(this, std::move(buf));
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 594a38b7b..18b716fdb 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -94,6 +94,8 @@ namespace RTLIL
 		STATIC_ID_END,
 	};
 
+
+
 	enum PortDir : unsigned char  {
 		PD_UNKNOWN = 0,
 		PD_INPUT = 1,
@@ -137,32 +139,7 @@ namespace RTLIL
 	struct PortBit;
 };
 
-// A small polymorphic handle representing src to be applied to an
-// AttrObject by a CellAdder method or set_src_attribute call. Holds
-// EITHER a pre-interned twine id (preferred — the destination just
-// retains the slot, no flatten/intern) OR a literal string ("@N" or a
-// raw path:line.col) for legacy callers. Implicit conversions cover
-// both shapes so existing string-passing call sites keep compiling
-// without changes; new code passing `cell->src_ref()` lands in the
-// cheap id branch.
-//
-// The caller must keep any pool slot named by `id` alive for the
-// duration of the call (typically: the source AttrObject still holds
-// it). Empty by default — passing a default-constructed SrcAttr to
-// set_src_attribute clears src_id_.
-struct RTLIL::SrcAttr
-{
-	Twine::Id id = Twine::Null;
-	std::string literal;
-
-	SrcAttr() = default;
-	SrcAttr(Twine::Id i) : id(i) {}
-	SrcAttr(std::string s) : literal(std::move(s)) {}
-	SrcAttr(const char *s) : literal(s ? s : "") {}
-	SrcAttr(std::string_view s) : literal(s) {}
-
-	bool empty() const { return id == Twine::Null && literal.empty(); }
-};
+using SrcAttr = TwineRef;
 
 // TODO clean up?
 extern int64_t signorm_ns;
@@ -1306,9 +1283,9 @@ public:
 
 struct RTLIL::ObjMeta
 {
-	Twine::Id src = Twine::Null;
+	TwineRef src = Twine::Null;
 	// RTLIL::IdString name;      // used by Module names
-	Twine::Id name_id = Twine::Null;  // used by Wire/Cell names (per-Design twines)
+	TwineRef name_id = Twine::Null;  // used by Wire/Cell names (per-Design twines)
 };
 
 struct RTLIL::AttrObject
@@ -1350,7 +1327,7 @@ struct RTLIL::NamedObject : public RTLIL::AttrObject
 	RTLIL::IdString name;
 };
 
-// Read-only masquerade for Wire::name. Reads materialise the Twine::Id in
+// Read-only masquerade for Wire::name. Reads materialise the TwineRef in
 // the owning Design's twines pool into a temporary IdString. Writes are
 // intentionally unsupported — use Module::rename(wire, new_name) instead.
 // Defined before Wire so it can be used as a [[no_unique_address]] member.
@@ -1916,8 +1893,8 @@ struct RTLIL::Selection
 	bool complete_selection;
 	// selection covers full design, not including boxed modules
 	bool full_selection;
-	pool<Twine::Id> selected_modules;
-	dict<Twine::Id, pool<Twine::Id>> selected_members;
+	pool<TwineRef> selected_modules;
+	dict<TwineRef, pool<TwineRef>> selected_members;
 	RTLIL::Design *current_design;
 
 	// create a new selection
@@ -1933,18 +1910,18 @@ struct RTLIL::Selection
 
 	// checks if the given module exists in the current design and is a
 	// boxed module, warning the user if the current design is not set
-	bool boxed_module(Twine::Id mod_name) const;
+	bool boxed_module(TwineRef mod_name) const;
 
 	// checks if the given module is included in this selection
-	bool selected_module(Twine::Id mod_name) const;
+	bool selected_module(TwineRef mod_name) const;
 
 	// checks if the given module is wholly included in this selection,
 	// i.e. not partially selected
-	bool selected_whole_module(Twine::Id mod_name) const;
+	bool selected_whole_module(TwineRef mod_name) const;
 
 	// checks if the given member from the given module is included in this
 	// selection
-	bool selected_member(Twine::Id mod_name, Twine::Id memb_name) const;
+	bool selected_member(TwineRef mod_name, TwineRef memb_name) const;
 
 	// optimizes this selection for the given design by:
 	// - removing non-existent modules and members, any boxed modules and
@@ -1966,7 +1943,7 @@ struct RTLIL::Selection
 	// add whole module to this selection
 	template<typename T1> void select(T1 *module) {
 		if (!selects_all() && selected_modules.count(module->meta_->name_id) == 0) {
-			Twine::Id name = module->meta_->name_id;
+			TwineRef name = module->meta_->name_id;
 			selected_modules.insert(name);
 			selected_members.erase(name);
 			if (module->get_blackbox_attribute())
@@ -2038,7 +2015,7 @@ struct RTLIL::Design
 	void sigNormalize(bool enable=true);
 
 	int refcount_modules_;
-	dict<Twine::Id, RTLIL::Module*> modules_;
+	dict<IdString, RTLIL::Module*> modules_;
 	std::vector<RTLIL::Binding*> bindings_;
 
 	TwinePool twines;
@@ -2051,10 +2028,10 @@ struct RTLIL::Design
 	RTLIL::ObjMeta *alloc_obj_meta();
 	void free_obj_meta(RTLIL::ObjMeta *m);
 
-	Twine::Id obj_src_id(const RTLIL::AttrObject *obj) const {
+	TwineRef obj_src_id(const RTLIL::AttrObject *obj) const {
 		return (obj->meta_ ? obj->meta_->src : Twine::Null);
 	}
-	void obj_set_src_id(RTLIL::AttrObject *obj, Twine::Id id);
+	void obj_set_src_id(RTLIL::AttrObject *obj, TwineRef id);
 	void obj_release_src(RTLIL::AttrObject *obj);
 
 	std::string obj_name(const RTLIL::AttrObject *obj) const {
@@ -2063,11 +2040,11 @@ struct RTLIL::Design
 	void obj_set_name(RTLIL::AttrObject *obj, RTLIL::IdString name);
 	void obj_release_name(RTLIL::AttrObject *obj);
 
-	// Wire/Cell names: stored as Twine::Id in twines.
-	Twine::Id obj_name_id(const RTLIL::AttrObject *obj) const {
+	// Wire/Cell names: stored as TwineRef in twines.
+	TwineRef obj_name_id(const RTLIL::AttrObject *obj) const {
 		return (obj->meta_ ? obj->meta_->name_id : Twine::Null);
 	}
-	void obj_set_name_id(RTLIL::AttrObject *obj, Twine::Id id);
+	void obj_set_name_id(RTLIL::AttrObject *obj, TwineRef id);
 	void obj_release_name_id(RTLIL::AttrObject *obj);
 
 	// Replacements for the methods that used to live on AttrObject and
@@ -2080,17 +2057,6 @@ struct RTLIL::Design
 			const TwinePool *src_pool);
 	void absorb_attrs(RTLIL::AttrObject *obj, dict<RTLIL::IdString, RTLIL::Const> &&buf);
 
-	// Resolve a stored src-attribute string to its flat path:line.col
-	// representation. If `raw` is a twine reference ("@N") returns
-	// twines.flatten(N); otherwise returns `raw` unchanged. Backends
-	// must call this whenever they emit src to a user-facing format.
-	std::string resolve_src(std::string_view raw) {
-		Twine* id = twines.get_ref(raw);
-		if (id == nullptr)
-			return std::string(raw);
-		return twines.flatten(id);
-	}
-
 	// Merge `source`'s src attribute into `target`'s src attribute via the
 	// twine pool. After the call `target` carries the combined "@N" ref.
 	// Handles every case: source has a "@N" ref → reuse that Id; source
@@ -2124,27 +2090,27 @@ struct RTLIL::Design
 
 	std::vector<RTLIL::Selection> selection_stack;
 	dict<RTLIL::IdString, RTLIL::Selection> selection_vars;
-	Twine::Id selected_active_module;
+	TwineRef selected_active_module;
 
 	Design();
 	~Design();
 
-	RTLIL::ObjRange<RTLIL::Module*, Twine::Id> modules();
+	RTLIL::ObjRange<RTLIL::Module*, TwineRef> modules();
 	RTLIL::Module *module(IdString name);
-	RTLIL::Module *module(Twine::Id name);
-	const RTLIL::Module *module(Twine::Id name) const;
+	// RTLIL::Module *module(TwineRef name);
+	// const RTLIL::Module *module(TwineRef name) const;
 	RTLIL::Module *top_module() const;
 
-	bool has(Twine::Id id) const {
+	bool has(IdString id) const {
 		return modules_.count(id) != 0;
 	}
 
 	void add(RTLIL::Module *module);
 	void add(RTLIL::Binding *binding);
 
-	RTLIL::Module *addModule(Twine::Id name);
+	RTLIL::Module *addModule(TwineRef name);
 	void remove(RTLIL::Module *module);
-	void rename(RTLIL::Module *module, Twine::Id new_name);
+	void rename(RTLIL::Module *module, TwineRef new_name);
 
 	void scratchpad_unset(const std::string &varname);
 
@@ -2169,15 +2135,15 @@ struct RTLIL::Design
 	void clone_into(RTLIL::Design *dst) const;
 
 	// checks if the given module is included in the current selection
-	bool selected_module(Twine::Id mod_name) const;
+	bool selected_module(TwineRef mod_name) const;
 
 	// checks if the given module is wholly included in the current
 	// selection, i.e. not partially selected
-	bool selected_whole_module(Twine::Id mod_name) const;
+	bool selected_whole_module(TwineRef mod_name) const;
 
 	// checks if the given member from the given module is included in the
 	// current selection
-	bool selected_member(Twine::Id mod_name, Twine::Id memb_name) const;
+	bool selected_member(TwineRef mod_name, TwineRef memb_name) const;
 
 	// checks if the given module is included in the current selection
 	bool selected_module(RTLIL::Module *mod) const;
@@ -2222,7 +2188,7 @@ struct RTLIL::Design
 
 	// is the given member of the given module in the current selection
 	template<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {
-		return selected_member(module->name, member->name);
+		return selected_member(module->meta_->name_id, member->meta_->name_id);
 	}
 
 	// add whole module to the current selection
@@ -2317,9 +2283,9 @@ public:
 
 	// Context-aware src helpers. Resolve Design via module->design and
 	// route to the per-Design meta vector; assert the wire is attached.
-	Twine::Id src_id() const;
-	Twine::Id src_ref() const { return src_id(); }
-	void set_src_id(Twine::Id id);
+	TwineRef src_id() const;
+	TwineRef src_ref() const { return src_id(); }
+	void set_src_id(TwineRef id);
 	void set_src_attribute(const RTLIL::SrcAttr &src);
 	std::string get_src_attribute() const;
 	// Transfer src from `source` verbatim (same pool). Asserts attached
@@ -2372,9 +2338,9 @@ struct RTLIL::Memory : public RTLIL::NamedObject
 
 	// Context-aware src helpers. Resolve Design via module->design and
 	// route to the per-Design meta vector; assert the memory is attached.
-	Twine::Id src_id() const;
-	Twine::Id src_ref() const { return src_id(); }
-	void set_src_id(Twine::Id id);
+	TwineRef src_id() const;
+	TwineRef src_ref() const { return src_id(); }
+	void set_src_id(TwineRef id);
 	void set_src_attribute(const RTLIL::SrcAttr &src);
 	std::string get_src_attribute() const;
 	void adopt_src_from(const RTLIL::AttrObject *source);
@@ -2420,32 +2386,32 @@ public:
 	void operator=(RTLIL::Cell &other) = delete;
 
 	RTLIL::Module *module;
-	RTLIL::IdString type;
+	IdString type;
 	dict<RTLIL::IdString, RTLIL::SigSpec> connections_;
 	dict<RTLIL::IdString, RTLIL::Const> parameters;
 
 	// Context-aware src helpers. Resolve Design via module->design and
 	// route to the per-Design meta vector; assert the cell is attached.
-	Twine::Id src_id() const;
-	Twine::Id src_ref() const { return src_id(); }
-	void set_src_id(Twine::Id id);
+	TwineRef src_id() const;
+	TwineRef src_ref() const { return src_id(); }
+	void set_src_id(TwineRef id);
 	void set_src_attribute(const RTLIL::SrcAttr &src);
 	std::string get_src_attribute() const;
 	void adopt_src_from(const RTLIL::AttrObject *source);
 	void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
 
 	// access cell ports
-	bool hasPort(RTLIL::IdString portname) const;
-	void unsetPort(RTLIL::IdString portname);
-	void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal);
-	const RTLIL::SigSpec &getPort(RTLIL::IdString portname) const;
-	const dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;
+	bool hasPort(TwineRef portname) const;
+	void unsetPort(TwineRef portname);
+	void setPort(TwineRef portname, RTLIL::SigSpec signal);
+	const RTLIL::SigSpec &getPort(TwineRef portname) const;
+	const dict<TwineRef, RTLIL::SigSpec> &connections() const;
 
 	// information about cell ports
 	bool known() const;
-	bool input(RTLIL::IdString portname) const;
-	bool output(RTLIL::IdString portname) const;
-	PortDir port_dir(RTLIL::IdString portname) const;
+	bool input(TwineRef portname) const;
+	bool output(TwineRef portname) const;
+	PortDir port_dir(TwineRef portname) const;
 
 	// access cell parameters
 	bool hasParam(RTLIL::IdString paramname) const;
@@ -2498,9 +2464,9 @@ struct RTLIL::CaseRule : public RTLIL::AttrObject
 	void setModuleRecursive(RTLIL::Module *m);
 
 	// Context-aware src helpers via module->design.
-	Twine::Id src_id() const;
-	Twine::Id src_ref() const { return src_id(); }
-	void set_src_id(Twine::Id id);
+	TwineRef src_id() const;
+	TwineRef src_ref() const { return src_id(); }
+	void set_src_id(TwineRef id);
 	void set_src_attribute(const RTLIL::SrcAttr &src);
 	std::string get_src_attribute() const;
 	void adopt_src_from(const RTLIL::AttrObject *source);
@@ -2526,9 +2492,9 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject
 	void setModuleRecursive(RTLIL::Module *m);
 
 	// Context-aware src helpers via module->design.
-	Twine::Id src_id() const;
-	Twine::Id src_ref() const { return src_id(); }
-	void set_src_id(Twine::Id id);
+	TwineRef src_id() const;
+	TwineRef src_ref() const { return src_id(); }
+	void set_src_id(TwineRef id);
 	void set_src_attribute(const RTLIL::SrcAttr &src);
 	std::string get_src_attribute() const;
 	void adopt_src_from(const RTLIL::AttrObject *source);
@@ -2551,9 +2517,9 @@ struct RTLIL::MemWriteAction : RTLIL::AttrObject
 	RTLIL::Const priority_mask;
 
 	// Context-aware src helpers via module->design.
-	Twine::Id src_id() const;
-	Twine::Id src_ref() const { return src_id(); }
-	void set_src_id(Twine::Id id);
+	TwineRef src_id() const;
+	TwineRef src_ref() const { return src_id(); }
+	void set_src_id(TwineRef id);
 	void set_src_attribute(const RTLIL::SrcAttr &src);
 	std::string get_src_attribute() const;
 	void adopt_src_from(const RTLIL::AttrObject *source);
@@ -2594,9 +2560,9 @@ public:
 
 	// Context-aware src helpers. Resolve Design via module->design and
 	// route to the per-Design meta vector; assert the process is attached.
-	Twine::Id src_id() const;
-	Twine::Id src_ref() const { return src_id(); }
-	void set_src_id(Twine::Id id);
+	TwineRef src_id() const;
+	TwineRef src_ref() const { return src_id(); }
+	void set_src_id(TwineRef id);
 	void set_src_attribute(const RTLIL::SrcAttr &src);
 	std::string get_src_attribute() const;
 	void adopt_src_from(const RTLIL::AttrObject *source);
@@ -2674,8 +2640,8 @@ inline Hasher RTLIL::SigBit::hash_into(Hasher h) const {
 inline Hasher RTLIL::SigBit::hash_top() const {
 	Hasher h;
 	if (wire) {
-		// Use the wire's name_id (Twine::Id) directly — avoids IdString materialisation.
-		Twine::Id name_id = wire->meta_ ? wire->meta_->name_id : Twine::Null;
+		// Use the wire's name_id (TwineRef) directly — avoids IdString materialisation.
+		TwineRef name_id = wire->meta_ ? wire->meta_->name_id : Twine::Null;
 		h.eat(name_id);
 		h.eat(offset);
 		return h;
@@ -2704,212 +2670,212 @@ class CellAdderMixin {
 public:
 	// The add* methods create a cell and return the created cell. All signals must exist in advance.
 
-	RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
 
-	RTLIL::Cell* addAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::Cell* addAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
 
-	RTLIL::Cell* addReduceAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addReduceOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addReduceXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::Cell* addReduceAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addReduceOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addReduceXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
 
-	RTLIL::Cell* addShl    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addShr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addSshl   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addSshr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addShift  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::Cell* addShl    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addShr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addSshl   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addSshr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addShift  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
 
-	RTLIL::Cell* addLt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addLe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addEq  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addNe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addGe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addGt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::Cell* addLt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addLe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addEq  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addNe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addGe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addGt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
 
-	RTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
 	// truncating division
-	RTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
 	// truncating modulo
-	RTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, TwineRef src = Twine::Null);
 
-	RTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
 
-	RTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addLogicOr  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::Cell* addLogicOr  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
 
-	RTLIL::Cell* addMux  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::Cell* addMux  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
 
-	RTLIL::Cell* addBweqx  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addBwmux  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::Cell* addBweqx  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addBwmux  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
 
-	RTLIL::Cell* addSlice  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addLut    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addLive   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addFair   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addCover  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addEquiv  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::Cell* addSlice  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, TwineRef src = Twine::Null);
+	RTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addLut    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, TwineRef src = Twine::Null);
+	RTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
+	RTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
+	RTLIL::Cell* addLive   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
+	RTLIL::Cell* addFair   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
+	RTLIL::Cell* addCover  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
+	RTLIL::Cell* addEquiv  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
 
-	RTLIL::Cell* addSr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addFf    (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addDff   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d,   const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addDffe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::Cell* addSr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
+	RTLIL::Cell* addFf    (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null);
+	RTLIL::Cell* addDff   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d,   const RTLIL::SigSpec &sig_q, bool clk_polarity = true, TwineRef src = Twine::Null);
+	RTLIL::Cell* addDffe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, TwineRef src = Twine::Null);
+	RTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
+	RTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
+	RTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
+	RTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
+	RTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null);
+	RTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null);
+	RTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
+	RTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
+	RTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
+	RTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, TwineRef src = Twine::Null);
+	RTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
+	RTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
 
-	RTLIL::Cell* addBufGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addNotGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addAndGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addNandGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addOrGate     (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addNorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addXorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addXnorGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addOrnotGate  (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addMuxGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addNmuxGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addAoi3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addOai3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addAoi4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addOai4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::Cell* addBufGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addNotGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addAndGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addNandGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addOrGate     (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addNorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addXorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addXnorGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addOrnotGate  (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addMuxGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addNmuxGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addAoi3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addOai3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addAoi4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
+	RTLIL::Cell* addOai4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
 
 	RTLIL::Cell* addSrGate     (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
-			const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addFfGate     (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addDffGate    (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addDffeGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+			const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
+	RTLIL::Cell* addFfGate     (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null);
+	RTLIL::Cell* addDffGate    (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, TwineRef src = Twine::Null);
+	RTLIL::Cell* addDffeGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, TwineRef src = Twine::Null);
 	RTLIL::Cell* addDffsrGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
-			RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+			RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
 	RTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
-			RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+			RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
 	RTLIL::Cell* addAdffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
-			bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+			bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
 	RTLIL::Cell* addAdffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
-			bool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+			bool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
 	RTLIL::Cell* addAldffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
-			const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+			const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null);
 	RTLIL::Cell* addAldffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
-			const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+			const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null);
 	RTLIL::Cell* addSdffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
-			bool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+			bool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
 	RTLIL::Cell* addSdffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
-			bool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+			bool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
 	RTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
-			bool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+			bool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
+	RTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, TwineRef src = Twine::Null);
 	RTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
-			bool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+			bool arst_value = false, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
 	RTLIL::Cell* addDlatchsrGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
-			RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+			RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
 
-	RTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null);
 
 	// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.
 
-	RTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
 
-	RTLIL::SigSpec And  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Or   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Xor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::SigSpec And  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Or   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Xor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
 
-	RTLIL::SigSpec ReduceAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec ReduceOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec ReduceXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::SigSpec ReduceAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec ReduceOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec ReduceXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
 
-	RTLIL::SigSpec Shl    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Shr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Sshl   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Sshr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Shift  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::SigSpec Shl    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Shr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Sshl   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Sshr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Shift  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
 
-	RTLIL::SigSpec Lt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Le  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Eq  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Ne  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Ge  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Gt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::SigSpec Lt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Le  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Eq  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Ne  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Ge  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Gt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
 
-	RTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
 	// truncating division
-	RTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
 	// truncating modulo
-	RTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, TwineRef src = Twine::Null);
 
-	RTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec LogicOr  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
+	RTLIL::SigSpec LogicOr  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
 
-	RTLIL::SigSpec Mux      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Pmux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Bmux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Demux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::SigSpec Mux      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Pmux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Bmux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Demux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
 
-	RTLIL::SigSpec Bweqx      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Bwmux      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::SigSpec Bweqx      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Bwmux      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
 
-	RTLIL::SigBit BufGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigBit NotGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigBit AndGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigBit NandGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigBit OrGate     (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigBit NorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigBit XorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigBit XnorGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigBit OrnotGate  (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigBit MuxGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigBit NmuxGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigBit Aoi3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigBit Oai3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigBit Aoi4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigBit Oai4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::SigBit BufGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, TwineRef src = Twine::Null);
+	RTLIL::SigBit NotGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, TwineRef src = Twine::Null);
+	RTLIL::SigBit AndGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
+	RTLIL::SigBit NandGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
+	RTLIL::SigBit OrGate     (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
+	RTLIL::SigBit NorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
+	RTLIL::SigBit XorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
+	RTLIL::SigBit XnorGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
+	RTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
+	RTLIL::SigBit OrnotGate  (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
+	RTLIL::SigBit MuxGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, TwineRef src = Twine::Null);
+	RTLIL::SigBit NmuxGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, TwineRef src = Twine::Null);
+	RTLIL::SigBit Aoi3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, TwineRef src = Twine::Null);
+	RTLIL::SigBit Oai3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, TwineRef src = Twine::Null);
+	RTLIL::SigBit Aoi4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, TwineRef src = Twine::Null);
+	RTLIL::SigBit Oai4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, TwineRef src = Twine::Null);
 };
 
 // Zero-size masquerade for Module::name. Reads/writes route through
@@ -2926,7 +2892,7 @@ struct RTLIL::ModuleNameMasq {
 	ModuleNameMasq(const ModuleNameMasq&) = delete;
 	ModuleNameMasq(ModuleNameMasq&&) = delete;
 	operator RTLIL::IdString() const;
-	operator Twine::Id() const;
+	operator TwineRef() const;
 	ModuleNameMasq& operator=(RTLIL::IdString id);
 	// Without this, `new_mod->name = src_mod->name` invokes the implicit
 	// copy-assign (no-op) instead of operator=(IdString), so the meta
@@ -2962,7 +2928,7 @@ struct RTLIL::Module : public RTLIL::NamedObject, public CellAdderMixin<RTLIL::M
 	friend struct RTLIL::Cell;
 	friend struct RTLIL::Design;
 
-	[[no_unique_address]] RTLIL::ModuleNameMasq name;
+	// [[no_unique_address]] RTLIL::ModuleNameMasq name;
 
 	Hasher::hash_t hashidx_;
 	[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
@@ -2979,8 +2945,8 @@ public:
 	int refcount_wires_;
 	int refcount_cells_;
 
-	dict<Twine::Id, RTLIL::Wire*> wires_;
-	dict<Twine::Id, RTLIL::Cell*> cells_;
+	dict<TwineRef, RTLIL::Wire*> wires_;
+	dict<TwineRef, RTLIL::Cell*> cells_;
 
 	std::vector<RTLIL::SigSig>   connections_;
 	std::vector<RTLIL::Binding*> bindings_;
@@ -2992,9 +2958,9 @@ public:
 
 	// Context-aware src helpers. Resolve Design via this->design and
 	// route to the per-Design meta vector; assert the module is attached.
-	Twine::Id src_id() const;
-	Twine::Id src_ref() const { return src_id(); }
-	void set_src_id(Twine::Id id);
+	TwineRef src_id() const;
+	TwineRef src_ref() const { return src_id(); }
+	void set_src_id(TwineRef id);
 	void set_src_attribute(const RTLIL::SrcAttr &src);
 	std::string get_src_attribute() const;
 	void adopt_src_from(const RTLIL::AttrObject *source);
@@ -3022,7 +2988,7 @@ public:
 	void new_connections(const std::vector<RTLIL::SigSig> &new_conn);
 	const std::vector<RTLIL::SigSig> &connections() const;
 
-	std::vector<RTLIL::IdString> ports;
+	std::vector<TwineRef> ports;
 	void fixup_ports();
 
 	pool<RTLIL::Cell *> buf_norm_cell_queue;
@@ -3095,41 +3061,27 @@ public:
 	}
 
 	// Primary (fast) overloads — key directly into the dict.
-	RTLIL::Wire* wire(Twine::Id id) {
+	RTLIL::Wire* wire(TwineRef id) {
 		auto it = wires_.find(id);
 		return it == wires_.end() ? nullptr : it->second;
 	}
-	RTLIL::Cell* cell(Twine::Id id) {
+	RTLIL::Cell* cell(TwineRef id) {
 		auto it = cells_.find(id);
 		return it == cells_.end() ? nullptr : it->second;
 	}
-	const RTLIL::Wire* wire(Twine::Id id) const {
+	const RTLIL::Wire* wire(TwineRef id) const {
 		auto it = wires_.find(id);
 		return it == wires_.end() ? nullptr : it->second;
 	}
-	const RTLIL::Cell* cell(Twine::Id id) const {
+	const RTLIL::Cell* cell(TwineRef id) const {
 		auto it = cells_.find(id);
 		return it == cells_.end() ? nullptr : it->second;
 	}
 
-	// IdString compatibility shims: look up via twines, then dispatch.
-	RTLIL::Wire* wire(const RTLIL::IdString &id) {
-		return wire(design->twines.lookup(id.str()));
-	}
-	RTLIL::Cell* cell(const RTLIL::IdString &id) {
-		return cell(design->twines.lookup(id.str()));
-	}
-	const RTLIL::Wire* wire(const RTLIL::IdString &id) const {
-		return wire(design->twines.lookup(id.str()));
-	}
-	const RTLIL::Cell* cell(const RTLIL::IdString &id) const {
-		return cell(design->twines.lookup(id.str()));
-	}
-
-	RTLIL::ObjRange<RTLIL::Wire*, Twine::Id> wires() { return RTLIL::ObjRange<RTLIL::Wire*, Twine::Id>(&wires_, &refcount_wires_); }
+	RTLIL::ObjRange<RTLIL::Wire*, TwineRef> wires() { return RTLIL::ObjRange<RTLIL::Wire*, TwineRef>(&wires_, &refcount_wires_); }
 	int wires_size() const { return wires_.size(); }
 	RTLIL::Wire* wire_at(int index) const { return wires_.element(index)->second; }
-	RTLIL::ObjRange<RTLIL::Cell*, Twine::Id> cells() { return RTLIL::ObjRange<RTLIL::Cell*, Twine::Id>(&cells_, &refcount_cells_); }
+	RTLIL::ObjRange<RTLIL::Cell*, TwineRef> cells() { return RTLIL::ObjRange<RTLIL::Cell*, TwineRef>(&cells_, &refcount_cells_); }
 	int cells_size() const { return cells_.size(); }
 	RTLIL::Cell* cell_at(int index) const { return cells_.element(index)->second; }
 
@@ -3152,15 +3104,15 @@ public:
 	RTLIL::IdString uniquify(RTLIL::IdString name, int &index);
 
 	// Primary overloads: name already interned in design->twines.
-	RTLIL::Wire *addWire(Twine::Id name, int width = 1);
-	RTLIL::Wire *addWire(Twine::Id name, const RTLIL::Wire *other);
+	RTLIL::Wire *addWire(TwineRef name, int width = 1);
+	RTLIL::Wire *addWire(TwineRef name, const RTLIL::Wire *other);
 	// IdString compatibility: interns name into twines, then dispatches.
 	RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
 	RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
 
 	// Primary overloads.
-	RTLIL::Cell *addCell(Twine::Id name, RTLIL::IdString type);
-	RTLIL::Cell *addCell(Twine::Id name, const RTLIL::Cell *other);
+	RTLIL::Cell *addCell(TwineRef name, RTLIL::IdString type);
+	RTLIL::Cell *addCell(TwineRef name, const RTLIL::Cell *other);
 	// IdString compatibility.
 	RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
 	RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
@@ -3173,22 +3125,22 @@ public:
 
 	// The add* methods create a cell and return the created cell. All signals must exist in advance.
 
-	RTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null);
 
 	// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.
 
-	RTLIL::SigSpec Anyconst  (RTLIL::IdString name, int width = 1, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Anyseq    (RTLIL::IdString name, int width = 1, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Allconst  (RTLIL::IdString name, int width = 1, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Allseq    (RTLIL::IdString name, int width = 1, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec Initstate (RTLIL::IdString name, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::SigSpec Anyconst  (RTLIL::IdString name, int width = 1, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Anyseq    (RTLIL::IdString name, int width = 1, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Allconst  (RTLIL::IdString name, int width = 1, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Allseq    (RTLIL::IdString name, int width = 1, TwineRef src = Twine::Null);
+	RTLIL::SigSpec Initstate (RTLIL::IdString name, TwineRef src = Twine::Null);
 
-	RTLIL::SigSpec SetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell*   addSetTag       (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec GetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::Cell*   addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec OriginalTag     (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
-	RTLIL::SigSpec FutureFF        (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const RTLIL::SrcAttr &src = RTLIL::SrcAttr());
+	RTLIL::SigSpec SetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, TwineRef src = Twine::Null);
+	RTLIL::Cell*   addSetTag       (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
+	RTLIL::SigSpec GetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, TwineRef src = Twine::Null);
+	RTLIL::Cell*   addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, TwineRef src = Twine::Null);
+	RTLIL::SigSpec OriginalTag     (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, TwineRef src = Twine::Null);
+	RTLIL::SigSpec FutureFF        (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, TwineRef src = Twine::Null);
 
 	std::string to_rtlil_str() const;
 #ifdef YOSYS_ENABLE_PYTHON
@@ -3324,7 +3276,7 @@ inline RTLIL::WireNameMasq::operator RTLIL::IdString() const {
 		reinterpret_cast<const char *>(this) - offsetof(RTLIL::Wire, name));
 	if (!w->module || !w->module->design || !w->meta_)
 		return RTLIL::IdString{};
-	Twine::Id id = w->meta_->name_id;
+	TwineRef id = w->meta_->name_id;
 	if (id == Twine::Null)
 		return RTLIL::IdString{};
 	return RTLIL::IdString(w->module->design->twines.flat_string(id));
@@ -3335,7 +3287,7 @@ inline RTLIL::CellNameMasq::operator RTLIL::IdString() const {
 		reinterpret_cast<const char *>(this) - offsetof(RTLIL::Cell, name));
 	if (!c->module || !c->module->design || !c->meta_)
 		return RTLIL::IdString{};
-	Twine::Id id = c->meta_->name_id;
+	TwineRef id = c->meta_->name_id;
 	if (id == Twine::Null)
 		return RTLIL::IdString{};
 	return RTLIL::IdString(c->module->design->twines.flat_string(id));
@@ -3347,7 +3299,7 @@ inline RTLIL::ModuleNameMasq::operator RTLIL::IdString() const {
 	return m->design ? m->design->obj_name(m) : std::string();
 }
 
-inline RTLIL::ModuleNameMasq::operator Twine::Id() const {
+inline RTLIL::ModuleNameMasq::operator TwineRef() const {
 	const RTLIL::Module *m = reinterpret_cast<const RTLIL::Module*>(
 		reinterpret_cast<const char*>(this) - offsetof(RTLIL::Module, name));
 	return m->design ? m->design->obj_src_id(m) : nullptr;
diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc
index 9312e7249..d549c0344 100644
--- a/kernel/rtlil_bufnorm.cc
+++ b/kernel/rtlil_bufnorm.cc
@@ -521,7 +521,7 @@ void RTLIL::Module::remove(RTLIL::Cell *cell)
 		cell->unsetPort(cell->connections_.begin()->first);
 
 	log_assert(cell->meta_ && cell->meta_->name_id != Twine::Null);
-	Twine::Id cell_id = cell->meta_->name_id;
+	TwineRef cell_id = cell->meta_->name_id;
 	log_assert(cells_.count(cell_id) != 0);
 	log_assert(refcount_cells_ == 0);
 	cells_.erase(cell_id);
@@ -1246,7 +1246,7 @@ void RTLIL::Cell::initIndex()
 	}
 }
 
-void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
+void RTLIL::Cell::setPort(TwineRef portname, RTLIL::SigSpec signal)
 {
 	bool is_input = false;
 	if (module && module->sig_norm_index != nullptr && !ignored_cell(type)) {
diff --git a/kernel/tclapi.cc b/kernel/tclapi.cc
index 7554d70b9..ce25d10d1 100644
--- a/kernel/tclapi.cc
+++ b/kernel/tclapi.cc
@@ -258,7 +258,7 @@ static int tcl_get_attr(ClientData, Tcl_Interp *interp, int argc, const char *ar
 		obj_id = RTLIL::escape_id(argv[i++]);
 	attr_id = RTLIL::escape_id(argv[i++]);
 
-	RTLIL::Module *mod = yosys_design->module(yosys_design->twines.lookup(mod_id));
+	RTLIL::Module *mod = yosys_design->module(mod_id);
 	if (!mod)
 		ERROR("module not found")
 
@@ -266,11 +266,13 @@ static int tcl_get_attr(ClientData, Tcl_Interp *interp, int argc, const char *ar
 	if (mod_flag) {
 		obj = mod;
 	} else {
-		obj = mod->wire(obj_id);
+		TwineSearch search(&yosys_design->twines);
+		auto obj_twine = search.find(obj_id);
+		obj = mod->wire(obj_twine);
 		if (!obj)
 			obj = mod->memories.at(obj_id, nullptr);
 		if (!obj)
-			obj = mod->cell(obj_id);
+			obj = mod->cell(obj_twine);
 		if (!obj)
 			obj = mod->processes.at(obj_id, nullptr);
 	}
@@ -321,7 +323,7 @@ static int tcl_has_attr(ClientData, Tcl_Interp *interp, int argc, const char *ar
 		obj_id = RTLIL::escape_id(argv[i++]);
 	attr_id = RTLIL::escape_id(argv[i++]);
 
-	RTLIL::Module *mod = yosys_design->module(yosys_design->twines.lookup(mod_id));
+	RTLIL::Module *mod = yosys_design->module(mod_id);
 	if (!mod)
 		ERROR("module not found")
 
@@ -329,11 +331,13 @@ static int tcl_has_attr(ClientData, Tcl_Interp *interp, int argc, const char *ar
 	if (mod_flag) {
 		obj = mod;
 	} else {
-		obj = mod->wire(obj_id);
+		TwineSearch search(&yosys_design->twines);
+		auto obj_twine = search.find(obj_id);
+		obj = mod->wire(obj_twine);
 		if (!obj)
 			obj = mod->memories.at(obj_id, nullptr);
 		if (!obj)
-			obj = mod->cell(obj_id);
+			obj = mod->cell(obj_twine);
 		if (!obj)
 			obj = mod->processes.at(obj_id, nullptr);
 	}
@@ -374,7 +378,7 @@ static int tcl_set_attr(ClientData, Tcl_Interp *interp, int objc, Tcl_Obj *const
 		obj_id = RTLIL::escape_id(Tcl_GetString(objv[i++]));
 	attr_id = RTLIL::escape_id(Tcl_GetString(objv[i++]));
 
-	RTLIL::Module *mod = yosys_design->module(yosys_design->twines.lookup(mod_id));
+	RTLIL::Module *mod = yosys_design->module(mod_id);
 	if (!mod)
 		ERROR("module not found")
 
@@ -382,11 +386,13 @@ static int tcl_set_attr(ClientData, Tcl_Interp *interp, int objc, Tcl_Obj *const
 	if (mod_flag) {
 		obj = mod;
 	} else {
-		obj = mod->wire(obj_id);
+		TwineSearch search(&yosys_design->twines);
+		auto obj_twine = search.find(obj_id);
+		obj = mod->wire(obj_twine);
 		if (!obj)
 			obj = mod->memories.at(obj_id, nullptr);
 		if (!obj)
-			obj = mod->cell(obj_id);
+			obj = mod->cell(obj_twine);
 		if (!obj)
 			obj = mod->processes.at(obj_id, nullptr);
 	}
@@ -451,11 +457,13 @@ static int tcl_get_param(ClientData, Tcl_Interp *interp, int argc, const char *a
 	cell_id = RTLIL::escape_id(argv[i++]);
 	param_id = RTLIL::escape_id(argv[i++]);
 
-	RTLIL::Module *mod = yosys_design->module(yosys_design->twines.lookup(mod_id));
+	RTLIL::Module *mod = yosys_design->module(mod_id);
 	if (!mod)
 		ERROR("module not found")
 
-	RTLIL::Cell *cell = mod->cell(cell_id);
+	TwineSearch search(&yosys_design->twines);
+	auto cell_twine = search.find(cell_id);
+	Cell* cell = mod->cell(cell_twine);
 	if (!cell)
 		ERROR("object not found")
 
@@ -497,11 +505,13 @@ static int tcl_set_param(ClientData, Tcl_Interp *interp, int objc, Tcl_Obj *cons
 	cell_id = RTLIL::escape_id(Tcl_GetString(objv[i++]));
 	param_id = RTLIL::escape_id(Tcl_GetString(objv[i++]));
 
-	RTLIL::Module *mod = yosys_design->module(yosys_design->twines.lookup(mod_id));
+	RTLIL::Module *mod = yosys_design->module(mod_id);
 	if (!mod)
 		ERROR("module not found")
 
-	RTLIL::Cell *cell = mod->cell(cell_id);
+	TwineSearch search(&yosys_design->twines);
+	auto cell_twine = search.find(cell_id);
+	RTLIL::Cell *cell = mod->cell(cell_twine);
 	if (!cell)
 		ERROR("object not found")
 
diff --git a/kernel/twine.cc b/kernel/twine.cc
index c899e3d55..732b25a77 100644
--- a/kernel/twine.cc
+++ b/kernel/twine.cc
@@ -3,557 +3,595 @@
 
 YOSYS_NAMESPACE_BEGIN
 
-TwinePool::TwinePool()
-    : leaf_index_(0, LeafHash{this}, LeafEq{this})
-    , suffix_index_(0, SuffixHash{this}, SuffixEq{this})
-    , concat_index_(0, ConcatHash{this}, ConcatEq{this})
-{}
+std::vector<Twine> TwinePool::globals_;
 
-TwinePool::TwinePool(const TwinePool &other)
-    : nodes_(other.nodes_)
-    , refcount_(other.refcount_)
-    , free_list_(other.free_list_)
-    , leaf_index_(0, LeafHash{this}, LeafEq{this})
-    , suffix_index_(0, SuffixHash{this}, SuffixEq{this})
-    , concat_index_(0, ConcatHash{this}, ConcatEq{this})
+// TwineRef twine_populate(std::string name) {
+// 	if (name[1] == '$') {
+// 		// Skip prepended '\'
+// 		name = name.substr(1);
+// 	}
+// 	TwinePool::globals_.push_back(Twine(name));
+// 	return &TwinePool::globals_.back();
+// }
+// void twine_prepopulate() {
+// 	int size = static_cast<short>(RTLIL::StaticId::STATIC_ID_END);
+// 	TwinePool::globals_.reserve(size);
+// 	TwinePool::globals_.push_back(Twine(""));
+// #define X(_id) twine_populate("\\" #_id);
+// #include "kernel/constids.inc"
+// #undef X
+// }
+
+// #define X(N) const TW TW::N{IDX_##N};
+// #include "kernel/constids.inc"
+// #undef X
+
+enum : short
 {
-	rebuild_indexes_();
-}
+    STATIC_ID_BEGIN = 0,
+#define X(N) IDX_##N,
+#include "kernel/constids.inc"
+#undef X
+    STATIC_ID_END
+};
 
-TwinePool &TwinePool::operator=(const TwinePool &other)
-{
-	if (this == &other)
-		return *this;
-	nodes_ = other.nodes_;
-	refcount_ = other.refcount_;
-	free_list_ = other.free_list_;
-	// Re-create the index sets with functors pointing to *this,
-	// then rebuild their contents from the (now-copied) nodes_.
-	leaf_index_ = std::unordered_set<Twine::Id, LeafHash, LeafEq>(
-		0, LeafHash{this}, LeafEq{this});
-	suffix_index_ = std::unordered_set<Twine::Id, SuffixHash, SuffixEq>(
-		0, SuffixHash{this}, SuffixEq{this});
-	concat_index_ = std::unordered_set<Twine::Id, ConcatHash, ConcatEq>(
-		0, ConcatHash{this}, ConcatEq{this});
-	rebuild_indexes_();
-	return *this;
-}
+#define X(N) const TW TW::N{IDX_##N};
+#include "kernel/constids.inc"
+#undef X
 
-void TwinePool::rebuild_indexes_()
-{
-	for (auto& n : nodes_) {
-		if (n.is_dead()) continue;
-		if (n.is_leaf())   leaf_index_.insert(&n);
-		else if (n.is_suffix()) suffix_index_.insert(&n);
-		else if (n.is_concat()) concat_index_.insert(&n);
-	}
-}
+// struct TwinePool {
+// 	colony<Twine>
+// };
 
-Twine::Id TwinePool::alloc_slot_(Twine &&node)
-{
-	if (!free_list_.empty()) {
-		// Pop the SMALLEST free id (not the most recent), so reuse order
-		// matches the original allocation order when an entire pool gets
-		// freed and rebuilt. That makes write_rtlil emit byte-identical
-		// "@N" refs across design -push;-pop and similar wholesale-clone
-		// cycles, even though the in-memory pool got renumbered through
-		// the free list.
-		// TODO nevermind, inefficient, solve in RTLIL frontend and backend
-		// auto it = std::min_element(free_list_.begin(), free_list_.end());
-		// Twine::Id id = *it;
-		// free_list_.erase(it);
-		Twine* id = free_list_.back();
-		*id = std::move(node);
-		// size_t idx = id - &nodes_.front();
-		// log_assert(idx > 0 && idx < refcount_.size());
-		// refcount_[idx] = 0;
-		refcount(id) = 0;
-		return id;
-	}
-	// Twine::Id id = static_cast<Twine::Id>(nodes_.size());
-	nodes_.push_back(std::move(node));
-	Twine* id = &nodes_.back();
-	refcount_.push_back(0);
-	return id;
-}
+// TwinePool::TwinePool()
+//     : index_(0, LeafHash{this}, LeafEq{this})
+// {}
 
-Twine::Id TwinePool::intern(std::string_view str)
-{
-	if (str.empty())
-		return Twine::Null;
-	// Transparent find: probes with string_view, no string allocation.
-	// TODO why are they split like this? Is this called on a hot path somewhere?
-	if (auto it = leaf_index_.find(str); it != leaf_index_.end()) {
-		retain(*it);
-		return *it;
-	}
-	if (auto it = suffix_index_.find(str); it != suffix_index_.end()) {
-		retain(*it);
-		return *it;
-	}
-	if (auto it = concat_index_.find(str); it != concat_index_.end()) {
-		retain(*it);
-		return *it;
-	}
-	Twine::Id id = alloc_slot_(Twine{std::string{str}});
-	leaf_index_.insert(id);
+// TwinePool::TwinePool(const TwinePool &other)
+//     : nodes_(other.nodes_)
+//     , refcount_(other.refcount_)
+//     , free_list_(other.free_list_)
+//     , leaf_index_(0, LeafHash{this}, LeafEq{this})
+//     , suffix_index_(0, SuffixHash{this}, SuffixEq{this})
+//     , concat_index_(0, ConcatHash{this}, ConcatEq{this})
+// {
+// 	rebuild_indexes_();
+// }
 
-	// size_t idx = id - &nodes_.front();
-	// log_assert(idx > 0 && idx < refcount_.size());
-	// refcount_[idx] = 1;
-	refcount(id) = 1;
-	return id;
-}
+// TwinePool &TwinePool::operator=(const TwinePool &other)
+// {
+// 	if (this == &other)
+// 		return *this;
+// 	nodes_ = other.nodes_;
+// 	refcount_ = other.refcount_;
+// 	free_list_ = other.free_list_;
+// 	// Re-create the index sets with functors pointing to *this,
+// 	// then rebuild their contents from the (now-copied) nodes_.
+// 	leaf_index_ = std::unordered_set<TwineRef, LeafHash, LeafEq>(
+// 		0, LeafHash{this}, LeafEq{this});
+// 	suffix_index_ = std::unordered_set<TwineRef, SuffixHash, SuffixEq>(
+// 		0, SuffixHash{this}, SuffixEq{this});
+// 	concat_index_ = std::unordered_set<TwineRef, ConcatHash, ConcatEq>(
+// 		0, ConcatHash{this}, ConcatEq{this});
+// 	rebuild_indexes_();
+// 	return *this;
+// }
 
-Twine* TwinePool::intern_suffix(Twine* parent, std::string_view tail)
-{
-	if (parent == Twine::Null)
-		return intern(tail);
-	log_assert(parent > &nodes_.front() && parent <= &nodes_.back() && !parent->is_dead());
-	log_assert(parent->is_flat() && "Suffix parent must be a flat node (Leaf or Suffix)");
-	if (tail.empty()) {
-		// No tail means "the same string as parent". Hand back a fresh
-		// owning ref on parent — semantically equivalent to a degenerate
-		// suffix node, but we avoid allocating a slot for it.
-		retain(parent);
-		return parent;
-	}
+// void TwinePool::rebuild_indexes_()
+// {
+// 	for (auto& n : nodes_) {
+// 		if (n.is_dead()) continue;
+// 		if (n.is_leaf())   leaf_index_.insert(&n);
+// 		else if (n.is_suffix()) suffix_index_.insert(&n);
+// 		else if (n.is_concat()) concat_index_.insert(&n);
+// 	}
+// }
 
-	// Transparent find: probes with (parent, string_view), no allocation.
-	SuffixKey key{parent, tail};
-	if (auto it = suffix_index_.find(key); it != suffix_index_.end()) {
-		retain(*it);
-		return *it;
-	}
+// TwineRef TwinePool::alloc_slot_(Twine &&node)
+// {
+// 	if (!free_list_.empty()) {
+// 		// Pop the SMALLEST free id (not the most recent), so reuse order
+// 		// matches the original allocation order when an entire pool gets
+// 		// freed and rebuilt. That makes write_rtlil emit byte-identical
+// 		// "@N" refs across design -push;-pop and similar wholesale-clone
+// 		// cycles, even though the in-memory pool got renumbered through
+// 		// the free list.
+// 		// TODO nevermind, inefficient, solve in RTLIL frontend and backend
+// 		// auto it = std::min_element(free_list_.begin(), free_list_.end());
+// 		// TwineRef id = *it;
+// 		// free_list_.erase(it);
+// 		Twine* id = free_list_.back();
+// 		*id = std::move(node);
+// 		// size_t idx = id - &nodes_.front();
+// 		// log_assert(idx > 0 && idx < refcount_.size());
+// 		// refcount_[idx] = 0;
+// 		refcount(id) = 0;
+// 		return id;
+// 	}
+// 	// TwineRef id = static_cast<TwineRef>(nodes_.size());
+// 	nodes_.push_back(std::move(node));
+// 	Twine* id = &nodes_.back();
+// 	refcount_.push_back(0);
+// 	return id;
+// }
 
-	// Internal child ref: the suffix node owns one ref on its parent.
-	retain(parent);
-	Twine::Id id = alloc_slot_(Twine{Twine::Suffix{parent, std::string{tail}}});
-	suffix_index_.insert(id);
-	refcount(id) = 1;
-	return id;
-}
+// TwineRef TwinePool::intern(std::string_view str)
+// {
+// 	if (str.empty())
+// 		return Twine::Null;
+// 	// Transparent find: probes with string_view, no string allocation.
+// 	// TODO why are they split like this? Is this called on a hot path somewhere?
+// 	if (auto it = leaf_index_.find(str); it != leaf_index_.end()) {
+// 		retain(*it);
+// 		return *it;
+// 	}
+// 	if (auto it = suffix_index_.find(str); it != suffix_index_.end()) {
+// 		retain(*it);
+// 		return *it;
+// 	}
+// 	if (auto it = concat_index_.find(str); it != concat_index_.end()) {
+// 		retain(*it);
+// 		return *it;
+// 	}
+// 	TwineRef id = alloc_slot_(Twine{std::string{str}});
+// 	leaf_index_.insert(id);
 
-Twine::Id TwinePool::concat(std::span<const Twine::Id> parts)
-{
-	// Flat invariant: a Concat node only ever holds flat children (Leaf
-	// or Suffix), never another Concat. Splice in concats' children
-	// directly so identical sets map to byte-equal child vectors
-	// regardless of how callers nested concats.
-	std::vector<Twine::Id> children;
-	children.reserve(parts.size());
-	pool<Twine::Id> seen;
-	auto push_flat = [&](Twine::Id flat_id) {
-		if (seen.insert(flat_id).second)
-			children.push_back(flat_id);
-	};
-	for (Twine::Id p : parts) {
-		if (p == Twine::Null)
-			continue;
-		// log_assert(p < nodes_.size() && !nodes_[p].is_dead());
-		const Twine &n = *p;
-		if (n.is_flat()) {
-			push_flat(p);
-		} else {
-			for (Twine::Id grandchild : n.children())
-				push_flat(grandchild);
-		}
-	}
+// 	// size_t idx = id - &nodes_.front();
+// 	// log_assert(idx > 0 && idx < refcount_.size());
+// 	// refcount_[idx] = 1;
+// 	refcount(id) = 1;
+// 	return id;
+// }
 
-	if (children.empty())
-		return Twine::Null;
-	if (children.size() == 1) {
-		retain(children.front());
-		return children.front();
-	}
+// Twine* TwinePool::intern_suffix(Twine* parent, std::string_view tail)
+// {
+// 	if (parent == Twine::Null)
+// 		return intern(tail);
+// 	log_assert(parent > &nodes_.front() && parent <= &nodes_.back() && !parent->is_dead());
+// 	log_assert(parent->is_flat() && "Suffix parent must be a flat node (Leaf or Suffix)");
+// 	if (tail.empty()) {
+// 		// No tail means "the same string as parent". Hand back a fresh
+// 		// owning ref on parent — semantically equivalent to a degenerate
+// 		// suffix node, but we avoid allocating a slot for it.
+// 		retain(parent);
+// 		return parent;
+// 	}
 
-	// Transparent find: probes with span, no vector allocation.
-	std::span<const Twine::Id> child_span{children};
-	if (auto it = concat_index_.find(child_span); it != concat_index_.end()) {
-		retain(*it);
-		return *it;
-	}
+// 	// Transparent find: probes with (parent, string_view), no allocation.
+// 	SuffixKey key{parent, tail};
+// 	if (auto it = suffix_index_.find(key); it != suffix_index_.end()) {
+// 		retain(*it);
+// 		return *it;
+// 	}
 
-	// Internal child refs: the concat node owns one ref on each child.
-	for (Twine::Id c : children)
-		retain(c);
-	Twine::Id id = alloc_slot_(Twine{std::move(children)});
-	concat_index_.insert(id);
-	refcount(id) = 1;
-	return id;
-}
+// 	// Internal child ref: the suffix node owns one ref on its parent.
+// 	retain(parent);
+// 	TwineRef id = alloc_slot_(Twine{Twine::Suffix{parent, std::string{tail}}});
+// 	suffix_index_.insert(id);
+// 	refcount(id) = 1;
+// 	return id;
+// }
 
-Twine::Id TwinePool::concat(Twine::Id a, Twine::Id b)
-{
-	std::array<Twine::Id, 2> pair{a, b};
-	return concat(std::span<const Twine::Id>{pair});
-}
+// TwineRef TwinePool::concat(std::span<const TwineRef> parts)
+// {
+// 	// Flat invariant: a Concat node only ever holds flat children (Leaf
+// 	// or Suffix), never another Concat. Splice in concats' children
+// 	// directly so identical sets map to byte-equal child vectors
+// 	// regardless of how callers nested concats.
+// 	std::vector<TwineRef> children;
+// 	children.reserve(parts.size());
+// 	pool<TwineRef> seen;
+// 	auto push_flat = [&](TwineRef flat_id) {
+// 		if (seen.insert(flat_id).second)
+// 			children.push_back(flat_id);
+// 	};
+// 	for (TwineRef p : parts) {
+// 		if (p == Twine::Null)
+// 			continue;
+// 		// log_assert(p < nodes_.size() && !nodes_[p].is_dead());
+// 		const Twine &n = *p;
+// 		if (n.is_flat()) {
+// 			push_flat(p);
+// 		} else {
+// 			for (TwineRef grandchild : n.children())
+// 				push_flat(grandchild);
+// 		}
+// 	}
 
-void TwinePool::retain(Twine::Id id)
-{
-	if (id == Twine::Null)
-		return;
-	refcount(id)++;
-}
+// 	if (children.empty())
+// 		return Twine::Null;
+// 	if (children.size() == 1) {
+// 		retain(children.front());
+// 		return children.front();
+// 	}
 
-void TwinePool::release(Twine::Id id)
-{
-	if (id == Twine::Null)
-		return;
-	// log_assert(id < nodes_.size() && !nodes_[id].is_dead());
-	log_assert(refcount(id) > 0);
-	if (--refcount(id) == 0)
-		destroy_slot_(id);
-}
+// 	// Transparent find: probes with span, no vector allocation.
+// 	std::span<const TwineRef> child_span{children};
+// 	if (auto it = concat_index_.find(child_span); it != concat_index_.end()) {
+// 		retain(*it);
+// 		return *it;
+// 	}
 
-size_t TwinePool::index(Twine::Id p) const
-{
-	return p - &nodes_.front();
-}
+// 	// Internal child refs: the concat node owns one ref on each child.
+// 	for (TwineRef c : children)
+// 		retain(c);
+// 	TwineRef id = alloc_slot_(Twine{std::move(children)});
+// 	concat_index_.insert(id);
+// 	refcount(id) = 1;
+// 	return id;
+// }
 
-uint32_t& TwinePool::refcount(Twine::Id id)
-{
-	log_assert(id != Twine::Null);
-	size_t idx = index(id);
-	log_assert(idx > 0 && idx < refcount_.size());
-	return refcount_[idx];
-}
+// TwineRef TwinePool::concat(TwineRef a, TwineRef b)
+// {
+// 	std::array<TwineRef, 2> pair{a, b};
+// 	return concat(std::span<const TwineRef>{pair});
+// }
 
-uint32_t TwinePool::refcount(Twine::Id id) const
-{
-	log_assert(id != Twine::Null);
-	size_t idx = id - &nodes_.front();
-	log_assert(idx > 0 && idx < refcount_.size());
-	return refcount_[idx];
-}
+// void TwinePool::retain(TwineRef id)
+// {
+// 	if (id == Twine::Null)
+// 		return;
+// 	refcount(id)++;
+// }
 
-bool TwinePool::is_alive(Twine::Id id) const
-{
-	if (id == Twine::Null)
-		return false;
-	return id >= &nodes_.front() && id <= &nodes_.back() && !id->is_dead();
-}
+// void TwinePool::release(TwineRef id)
+// {
+// 	if (id == Twine::Null)
+// 		return;
+// 	// log_assert(id < nodes_.size() && !nodes_[id].is_dead());
+// 	log_assert(refcount(id) > 0);
+// 	if (--refcount(id) == 0)
+// 		destroy_slot_(id);
+// }
 
-void TwinePool::destroy_slot_(Twine::Id id)
-{
-	Twine &n = *id;
-	if (n.is_leaf()) {
-		// Erase by id: functor reads nodes_[id].leaf() before we tombstone.
-		leaf_index_.erase(id);
-	} else if (n.is_concat()) {
-		// Erase by id first (while data is still readable), then capture
-		// children by move so iteration is stable across recursive release.
-		concat_index_.erase(id);
-		std::vector<Twine::Id> children =
-			std::move(std::get<std::vector<Twine::Id>>(n.data));
-		n.data = std::monostate{};
-		free_list_.push_back(id);
-		for (Twine::Id c : children)
-			release(c);
-		return;
-	} else if (n.is_suffix()) {
-		// Same pattern: erase first, then move data for deferred release.
-		suffix_index_.erase(id);
-		Twine::Suffix s = std::move(std::get<Twine::Suffix>(n.data));
-		n.data = std::monostate{};
-		free_list_.push_back(id);
-		release(s.parent);
-		return;
-	}
-	n.data = std::monostate{};
-	free_list_.push_back(id);
-}
+// size_t TwinePool::index(TwineRef p) const
+// {
+// 	return p - &nodes_.front();
+// }
 
-Twine::Id TwinePool::lookup(std::string_view sv) const
-{
-	if (sv.empty())
-		return Twine::Null;
-	auto it = leaf_index_.find(sv);
-	return (it != leaf_index_.end()) ? *it : Twine::Null;
-}
+// uint32_t& TwinePool::refcount(TwineRef id)
+// {
+// 	log_assert(id != Twine::Null);
+// 	size_t idx = index(id);
+// 	log_assert(idx > 0 && idx < refcount_.size());
+// 	return refcount_[idx];
+// }
 
-char TwinePool::first_char(Twine::Id id) const
-{
-	log_assert(id != Twine::Null && id > &nodes_.front() && id <= &nodes_.back() && !id->is_dead());
-	// Walk suffix parents to reach the root leaf, then return its first char.
-	while (id->is_suffix())
-		id = id->suffix().parent;
-	const std::string &s = id->leaf();
-	// TODO seems wrong for concate
-	return s.empty() ? '\0' : s.front();
-}
+// uint32_t TwinePool::refcount(TwineRef id) const
+// {
+// 	log_assert(id != Twine::Null);
+// 	size_t idx = id - &nodes_.front();
+// 	log_assert(idx > 0 && idx < refcount_.size());
+// 	return refcount_[idx];
+// }
 
-void TwinePool::collect_leaves(Twine::Id id, pool<std::string> &out) const
-{
-	if (id == Twine::Null)
-		return;
-	const Twine &n = *id;
-	if (n.is_dead())
-		return;
-	if (n.is_leaf()) {
-		out.insert(n.leaf());
-		return;
-	}
-	if (n.is_suffix()) {
-		// A suffix is semantically a single flat string. Materialize it
-		// and insert into the set just like a leaf.
-		out.insert(flat_string_(id));
-		return;
-	}
-	for (Twine::Id c : n.children())
-		collect_leaves(c, out);
-}
+// bool TwinePool::is_alive(TwineRef id) const
+// {
+// 	if (id == Twine::Null)
+// 		return false;
+// 	return id >= &nodes_.front() && id <= &nodes_.back() && !id->is_dead();
+// }
 
-std::string TwinePool::flat_string_(Twine::Id id) const
-{
-	// Walk the parent chain iteratively to avoid recursion depth concerns
-	// on deep suffix trees. Collect tails (and the root leaf) then stitch
-	// in root-to-tail order.
-	log_assert(id != Twine::Null);
-	std::vector<std::string_view> parts;
-	while (true) {
-		const Twine &n = *id;
-		if (n.is_leaf()) {
-			parts.push_back(n.leaf());
-			break;
-		}
-		log_assert(n.is_suffix());
-		parts.push_back(n.suffix().tail);
-		id = n.suffix().parent;
-	}
-	size_t total = 0;
-	for (auto p : parts)
-		total += p.size();
-	std::string out;
-	out.reserve(total);
-	for (auto it = parts.rbegin(); it != parts.rend(); ++it)
-		out.append(*it);
-	return out;
-}
+// void TwinePool::destroy_slot_(TwineRef id)
+// {
+// 	Twine &n = *id;
+// 	if (n.is_leaf()) {
+// 		// Erase by id: functor reads nodes_[id].leaf() before we tombstone.
+// 		leaf_index_.erase(id);
+// 	} else if (n.is_concat()) {
+// 		// Erase by id first (while data is still readable), then capture
+// 		// children by move so iteration is stable across recursive release.
+// 		concat_index_.erase(id);
+// 		std::vector<TwineRef> children =
+// 			std::move(std::get<std::vector<TwineRef>>(n.data));
+// 		n.data = std::monostate{};
+// 		free_list_.push_back(id);
+// 		for (TwineRef c : children)
+// 			release(c);
+// 		return;
+// 	} else if (n.is_suffix()) {
+// 		// Same pattern: erase first, then move data for deferred release.
+// 		suffix_index_.erase(id);
+// 		Twine::Suffix s = std::move(std::get<Twine::Suffix>(n.data));
+// 		n.data = std::monostate{};
+// 		free_list_.push_back(id);
+// 		release(s.parent);
+// 		return;
+// 	}
+// 	n.data = std::monostate{};
+// 	free_list_.push_back(id);
+// }
 
-std::string TwinePool::flatten(Twine::Id id, char sep) const
-{
-	if (id == Twine::Null)
-		return {};
-	pool<std::string> leaves;
-	collect_leaves(id, leaves);
-	std::string out;
-	for (const auto &s : leaves) {
-		if (s.empty())
-			continue;
-		if (!out.empty())
-			out += sep;
-		out += s;
-	}
-	return out;
-}
+// TwineRef TwinePool::lookup(std::string_view sv) const
+// {
+// 	if (sv.empty())
+// 		return Twine::Null;
+// 	auto it = leaf_index_.find(sv);
+// 	return (it != leaf_index_.end()) ? *it : Twine::Null;
+// }
 
-std::string TwinePool::format_ref(Twine::Id id) const
-{
-	if (id == Twine::Null)
-		return {};
-	size_t i = index(id);
-	return "@" + std::to_string(i);
-}
+// char TwinePool::first_char(TwineRef id) const
+// {
+// 	log_assert(id != Twine::Null && id > &nodes_.front() && id <= &nodes_.back() && !id->is_dead());
+// 	// Walk suffix parents to reach the root leaf, then return its first char.
+// 	while (id->is_suffix())
+// 		id = id->suffix().parent;
+// 	const std::string &s = id->leaf();
+// 	// TODO seems wrong for concate
+// 	return s.empty() ? '\0' : s.front();
+// }
 
-std::optional<size_t> TwinePool::parse_ref(std::string_view s)
-{
-	if (s.size() < 2 || s[0] != '@')
-		return std::nullopt;
-	uint64_t v = 0;
-	for (size_t i = 1; i < s.size(); i++) {
-		char c = s[i];
-		if (c < '0' || c > '9')
-			return std::nullopt;
-		v = v * 10 + static_cast<uint64_t>(c - '0');
-	}
-	return v;
-}
-Twine::Id TwinePool::get_ref(std::string_view s)
-{
-	if (auto idx = parse_ref(s))
-		return &nodes_.front() + *idx;
-	return nullptr;
-}
+// void TwinePool::collect_leaves(TwineRef id, pool<std::string> &out) const
+// {
+// 	if (id == Twine::Null)
+// 		return;
+// 	const Twine &n = *id;
+// 	if (n.is_dead())
+// 		return;
+// 	if (n.is_leaf()) {
+// 		out.insert(n.leaf());
+// 		return;
+// 	}
+// 	if (n.is_suffix()) {
+// 		// A suffix is semantically a single flat string. Materialize it
+// 		// and insert into the set just like a leaf.
+// 		out.insert(flat_string_(id));
+// 		return;
+// 	}
+// 	for (TwineRef c : n.children())
+// 		collect_leaves(c, out);
+// }
 
-void TwinePool::dump(const char *banner) const
-{
-	if (banner)
-		log("%s (%zu live nodes: %zu leaves, %zu suffixes, %zu concats, %zu free slots)\n",
-				banner, nodes_.size() - free_list_.size(),
-				leaf_index_.size(), suffix_index_.size(),
-				concat_index_.size(), free_list_.size());
-	for_each_live([&](Twine::Id id, const Twine &n) {
-		if (n.is_leaf()) {
-			log("  @%u leaf rc=%u %s\n", id, refcount(id), n.leaf().c_str());
-		} else if (n.is_suffix()) {
-			log("  @%u suffix rc=%u @%u + %s\n", id, refcount(id),
-					n.suffix().parent, n.suffix().tail.c_str());
-		} else {
-			std::string children;
-			for (Twine::Id c : n.children()) {
-				if (!children.empty())
-					children += ", ";
-				children += format_ref(c);
-			}
-			log("  @%u concat rc=%u [%s]\n", id, refcount(id), children.c_str());
-		}
-	});
-}
+// std::string TwinePool::flat_string_(TwineRef id) const
+// {
+// 	// Walk the parent chain iteratively to avoid recursion depth concerns
+// 	// on deep suffix trees. Collect tails (and the root leaf) then stitch
+// 	// in root-to-tail order.
+// 	log_assert(id != Twine::Null);
+// 	std::vector<std::string_view> parts;
+// 	while (true) {
+// 		const Twine &n = *id;
+// 		if (n.is_leaf()) {
+// 			parts.push_back(n.leaf());
+// 			break;
+// 		}
+// 		log_assert(n.is_suffix());
+// 		parts.push_back(n.suffix().tail);
+// 		id = n.suffix().parent;
+// 	}
+// 	size_t total = 0;
+// 	for (auto p : parts)
+// 		total += p.size();
+// 	std::string out;
+// 	out.reserve(total);
+// 	for (auto it = parts.rbegin(); it != parts.rend(); ++it)
+// 		out.append(*it);
+// 	return out;
+// }
 
-dict<Twine::Id, Twine::Id> TwinePool::gc(const pool<Twine::Id> &live)
-{
-	// Closure: mark every node reachable from `live`. Concat children
-	// (Leaf or Suffix) and Suffix parents (Leaf or Suffix) are both
-	// followed. With Suffix nodes chains can be more than one step deep,
-	// so use a worklist rather than a single BFS step.
-	pool<Twine::Id> reachable;
-	std::vector<Twine::Id> work;
-	for (Twine::Id id : live) {
-		if (!id || id->is_dead())
-			continue;
-		if (reachable.insert(id).second)
-			work.push_back(id);
-	}
-	while (!work.empty()) {
-		Twine::Id id = work.back();
-		work.pop_back();
-		const Twine &n = *id;
-		if (n.is_concat()) {
-			for (Twine::Id c : n.children())
-				if (reachable.insert(c).second)
-					work.push_back(c);
-		} else if (n.is_suffix()) {
-			Twine::Id p = n.suffix().parent;
-			if (reachable.insert(p).second)
-				work.push_back(p);
-		}
-	}
+// std::string TwinePool::flatten(TwineRef id, char sep) const
+// {
+// 	if (id == Twine::Null)
+// 		return {};
+// 	pool<std::string> leaves;
+// 	collect_leaves(id, leaves);
+// 	std::string out;
+// 	for (const auto &s : leaves) {
+// 		if (s.empty())
+// 			continue;
+// 		if (!out.empty())
+// 			out += sep;
+// 		out += s;
+// 	}
+// 	return out;
+// }
 
-	// Rebuild the pool from scratch using temporary storage; process flats
-	// before concats so child lookups can resolve.
-	std::vector<Twine> new_nodes;
-	std::vector<uint32_t> new_refcount;
-	dict<Twine::Id, Twine::Id> remap;
+// std::string TwinePool::format_ref(TwineRef id) const
+// {
+// 	if (id == Twine::Null)
+// 		return {};
+// 	size_t i = index(id);
+// 	return "@" + std::to_string(i);
+// }
 
-	// Helper: insert a leaf into new_nodes, dedup by string.
-	// dict<std::string, Twine::Id> new_leaf_map;
-	for (Twine::Id old_id : reachable) {
-		const Twine &n = *old_id;
-		if (n.is_leaf())
-			remap[old_id] = intern(n.leaf());
-	}
+// std::optional<size_t> TwinePool::parse_ref(std::string_view s)
+// {
+// 	if (s.size() < 2 || s[0] != '@')
+// 		return std::nullopt;
+// 	uint64_t v = 0;
+// 	for (size_t i = 1; i < s.size(); i++) {
+// 		char c = s[i];
+// 		if (c < '0' || c > '9')
+// 			return std::nullopt;
+// 		v = v * 10 + static_cast<uint64_t>(c - '0');
+// 	}
+// 	return v;
+// }
+// TwineRef TwinePool::get_ref(std::string_view s)
+// {
+// 	if (auto idx = parse_ref(s))
+// 		return &nodes_.front() + *idx;
+// 	return nullptr;
+// }
 
-	std::function<Twine::Id(Twine::Id)> remap_flat = [&](Twine::Id old_id) -> Twine::Id {
-		if (auto it = remap.find(old_id); it != remap.end())
-			return it->second;
-		const Twine &n = *old_id;
-		log_assert(n.is_suffix());
-		Twine::Id new_parent = remap_flat(n.suffix().parent);
-		// Dedup suffix nodes in the new pool.
-		for (auto& i : new_nodes) {
-			if (i.is_suffix()) {
-				const auto &s = i.suffix();
-				if (s.parent == new_parent && s.tail == n.suffix().tail) {
-					remap[old_id] = &i;
-					return &i;
-				}
-			}
-		}
-		// Twine::Id new_id = static_cast<Twine::Id>(new_nodes.size());
-		new_nodes.push_back(Twine{Twine::Suffix{new_parent, n.suffix().tail}});
-		Twine::Id new_id = &new_nodes.back();
-		new_refcount.push_back(0);
-		remap[old_id] = new_id;
-		return new_id;
-	};
+// void TwinePool::dump(const char *banner) const
+// {
+// 	if (banner)
+// 		log("%s (%zu live nodes: %zu leaves, %zu suffixes, %zu concats, %zu free slots)\n",
+// 				banner, nodes_.size() - free_list_.size(),
+// 				leaf_index_.size(), suffix_index_.size(),
+// 				concat_index_.size(), free_list_.size());
+// 	for_each_live([&](TwineRef id, const Twine &n) {
+// 		if (n.is_leaf()) {
+// 			log("  @%u leaf rc=%u %s\n", id, refcount(id), n.leaf().c_str());
+// 		} else if (n.is_suffix()) {
+// 			log("  @%u suffix rc=%u @%u + %s\n", id, refcount(id),
+// 					n.suffix().parent, n.suffix().tail.c_str());
+// 		} else {
+// 			std::string children;
+// 			for (TwineRef c : n.children()) {
+// 				if (!children.empty())
+// 					children += ", ";
+// 				children += format_ref(c);
+// 			}
+// 			log("  @%u concat rc=%u [%s]\n", id, refcount(id), children.c_str());
+// 		}
+// 	});
+// }
 
-	for (Twine::Id old_id : reachable) {
-		const Twine &n = *old_id;
-		if (n.is_suffix() && remap.find(old_id) == remap.end())
-			remap_flat(old_id);
-	}
+// dict<TwineRef, TwineRef> TwinePool::gc(const pool<TwineRef> &live)
+// {
+// 	// Closure: mark every node reachable from `live`. Concat children
+// 	// (Leaf or Suffix) and Suffix parents (Leaf or Suffix) are both
+// 	// followed. With Suffix nodes chains can be more than one step deep,
+// 	// so use a worklist rather than a single BFS step.
+// 	pool<TwineRef> reachable;
+// 	std::vector<TwineRef> work;
+// 	for (TwineRef id : live) {
+// 		if (!id || id->is_dead())
+// 			continue;
+// 		if (reachable.insert(id).second)
+// 			work.push_back(id);
+// 	}
+// 	while (!work.empty()) {
+// 		TwineRef id = work.back();
+// 		work.pop_back();
+// 		const Twine &n = *id;
+// 		if (n.is_concat()) {
+// 			for (TwineRef c : n.children())
+// 				if (reachable.insert(c).second)
+// 					work.push_back(c);
+// 		} else if (n.is_suffix()) {
+// 			TwineRef p = n.suffix().parent;
+// 			if (reachable.insert(p).second)
+// 				work.push_back(p);
+// 		}
+// 	}
 
-	// Dedup concat nodes by child vector.
-	dict<std::vector<Twine::Id>, Twine::Id> new_concat_map;
-	for (Twine::Id old_id : reachable) {
-		const Twine &n = *old_id;
-		if (!n.is_concat())
-			continue;
-		std::vector<Twine::Id> children;
-		children.reserve(n.children().size());
-		for (Twine::Id c : n.children())
-			children.push_back(remap.at(c));
-		if (auto it = new_concat_map.find(children); it != new_concat_map.end()) {
-			remap[old_id] = it->second;
-		} else {
-			// Twine::Id new_id = static_cast<Twine::Id>(new_nodes.size());
-			new_nodes.push_back(Twine{children});
-			Twine::Id new_id = &new_nodes.back();
-			new_refcount.push_back(0);
-			new_concat_map[std::get<std::vector<Twine::Id>>(new_nodes.back().data)] = new_id;
-			remap[old_id] = new_id;
-		}
-	}
+// 	// Rebuild the pool from scratch using temporary storage; process flats
+// 	// before concats so child lookups can resolve.
+// 	std::vector<Twine> new_nodes;
+// 	std::vector<uint32_t> new_refcount;
+// 	dict<TwineRef, TwineRef> remap;
+
+// 	// Helper: insert a leaf into new_nodes, dedup by string.
+// 	// dict<std::string, TwineRef> new_leaf_map;
+// 	for (TwineRef old_id : reachable) {
+// 		const Twine &n = *old_id;
+// 		if (n.is_leaf())
+// 			remap[old_id] = intern(n.leaf());
+// 	}
+
+// 	std::function<TwineRef(TwineRef)> remap_flat = [&](TwineRef old_id) -> TwineRef {
+// 		if (auto it = remap.find(old_id); it != remap.end())
+// 			return it->second;
+// 		const Twine &n = *old_id;
+// 		log_assert(n.is_suffix());
+// 		TwineRef new_parent = remap_flat(n.suffix().parent);
+// 		// Dedup suffix nodes in the new pool.
+// 		for (auto& i : new_nodes) {
+// 			if (i.is_suffix()) {
+// 				const auto &s = i.suffix();
+// 				if (s.parent == new_parent && s.tail == n.suffix().tail) {
+// 					remap[old_id] = &i;
+// 					return &i;
+// 				}
+// 			}
+// 		}
+// 		// TwineRef new_id = static_cast<TwineRef>(new_nodes.size());
+// 		new_nodes.push_back(Twine{Twine::Suffix{new_parent, n.suffix().tail}});
+// 		TwineRef new_id = &new_nodes.back();
+// 		new_refcount.push_back(0);
+// 		remap[old_id] = new_id;
+// 		return new_id;
+// 	};
+
+// 	for (TwineRef old_id : reachable) {
+// 		const Twine &n = *old_id;
+// 		if (n.is_suffix() && remap.find(old_id) == remap.end())
+// 			remap_flat(old_id);
+// 	}
+
+// 	// Dedup concat nodes by child vector.
+// 	dict<std::vector<TwineRef>, TwineRef> new_concat_map;
+// 	for (TwineRef old_id : reachable) {
+// 		const Twine &n = *old_id;
+// 		if (!n.is_concat())
+// 			continue;
+// 		std::vector<TwineRef> children;
+// 		children.reserve(n.children().size());
+// 		for (TwineRef c : n.children())
+// 			children.push_back(remap.at(c));
+// 		if (auto it = new_concat_map.find(children); it != new_concat_map.end()) {
+// 			remap[old_id] = it->second;
+// 		} else {
+// 			// TwineRef new_id = static_cast<TwineRef>(new_nodes.size());
+// 			new_nodes.push_back(Twine{children});
+// 			TwineRef new_id = &new_nodes.back();
+// 			new_refcount.push_back(0);
+// 			new_concat_map[std::get<std::vector<TwineRef>>(new_nodes.back().data)] = new_id;
+// 			remap[old_id] = new_id;
+// 		}
+// 	}
 
 
 
-	// Swap in the new storage and rebuild the intrusive indexes.
-	nodes_ = std::move(new_nodes);
-	refcount_ = std::move(new_refcount);
+// 	// Swap in the new storage and rebuild the intrusive indexes.
+// 	nodes_ = std::move(new_nodes);
+// 	refcount_ = std::move(new_refcount);
 
-	// Refcounts in the rebuilt pool.
-	for (Twine::Id old_id : live) {
-		auto it = remap.find(old_id);
-		if (it != remap.end())
-			refcount(it->second)++;
-	}
-	for (size_t i = 0; i < nodes_.size(); i++) {
-		if (nodes_[i].is_concat()) {
-			for (Twine::Id c : nodes_[i].children())
-				refcount(c)++;
-		} else if (nodes_[i].is_suffix()) {
-			refcount(nodes_[i].suffix().parent)++;
-		}
-	}
+// 	// Refcounts in the rebuilt pool.
+// 	for (TwineRef old_id : live) {
+// 		auto it = remap.find(old_id);
+// 		if (it != remap.end())
+// 			refcount(it->second)++;
+// 	}
+// 	for (size_t i = 0; i < nodes_.size(); i++) {
+// 		if (nodes_[i].is_concat()) {
+// 			for (TwineRef c : nodes_[i].children())
+// 				refcount(c)++;
+// 		} else if (nodes_[i].is_suffix()) {
+// 			refcount(nodes_[i].suffix().parent)++;
+// 		}
+// 	}
 
-	free_list_.clear();
-	leaf_index_ = std::unordered_set<Twine::Id, LeafHash, LeafEq>(
-		0, LeafHash{this}, LeafEq{this});
-	suffix_index_ = std::unordered_set<Twine::Id, SuffixHash, SuffixEq>(
-		0, SuffixHash{this}, SuffixEq{this});
-	concat_index_ = std::unordered_set<Twine::Id, ConcatHash, ConcatEq>(
-		0, ConcatHash{this}, ConcatEq{this});
-	rebuild_indexes_();
-	return remap;
-}
+// 	free_list_.clear();
+// 	leaf_index_ = std::unordered_set<TwineRef, LeafHash, LeafEq>(
+// 		0, LeafHash{this}, LeafEq{this});
+// 	suffix_index_ = std::unordered_set<TwineRef, SuffixHash, SuffixEq>(
+// 		0, SuffixHash{this}, SuffixEq{this});
+// 	concat_index_ = std::unordered_set<TwineRef, ConcatHash, ConcatEq>(
+// 		0, ConcatHash{this}, ConcatEq{this});
+// 	rebuild_indexes_();
+// 	return remap;
+// }
 
-Twine::Id TwinePool::copy_from(const TwinePool &src, Twine::Id src_id)
-{
-	if (src_id == Twine::Null)
-		return Twine::Null;
-	// log_assert(src_id < src.nodes_.size() && !src.nodes_[src_id].is_dead());
-	const Twine &n = *src_id;
-	if (n.is_leaf())
-		return intern(n.leaf());
-	if (n.is_suffix()) {
-		Twine::Id new_parent = copy_from(src, n.suffix().parent);
-		Twine::Id result = intern_suffix(new_parent, n.suffix().tail);
-		// intern_suffix retained the parent internally; the caller-side
-		// +1 ref from copy_from(parent) is surplus.
-		release(new_parent);
-		return result;
-	}
-	std::vector<Twine::Id> children;
-	children.reserve(n.children().size());
-	for (Twine::Id c : n.children())
-		children.push_back(copy_from(src, c));
-	Twine::Id result = concat(std::span<const Twine::Id>{children});
-	// concat retained each child internally; the caller-side +1 refs from
-	// copy_from(child) are surplus.
-	for (Twine::Id c : children)
-		release(c);
-	return result;
-}
+// TwineRef TwinePool::copy_from(const TwinePool &src, TwineRef src_id)
+// {
+// 	if (src_id == Twine::Null)
+// 		return Twine::Null;
+// 	// log_assert(src_id < src.nodes_.size() && !src.nodes_[src_id].is_dead());
+// 	const Twine &n = *src_id;
+// 	if (n.is_leaf())
+// 		return intern(n.leaf());
+// 	if (n.is_suffix()) {
+// 		TwineRef new_parent = copy_from(src, n.suffix().parent);
+// 		TwineRef result = intern_suffix(new_parent, n.suffix().tail);
+// 		// intern_suffix retained the parent internally; the caller-side
+// 		// +1 ref from copy_from(parent) is surplus.
+// 		release(new_parent);
+// 		return result;
+// 	}
+// 	std::vector<TwineRef> children;
+// 	children.reserve(n.children().size());
+// 	for (TwineRef c : n.children())
+// 		children.push_back(copy_from(src, c));
+// 	TwineRef result = concat(std::span<const TwineRef>{children});
+// 	// concat retained each child internally; the caller-side +1 refs from
+// 	// copy_from(child) are surplus.
+// 	for (TwineRef c : children)
+// 		release(c);
+// 	return result;
+// }
 
 YOSYS_NAMESPACE_END
diff --git a/kernel/twine.h b/kernel/twine.h
index cf786be3f..8f15f1e79 100644
--- a/kernel/twine.h
+++ b/kernel/twine.h
@@ -2,7 +2,9 @@
 #define YOSYS_TWINE_H
 
 #include "kernel/yosys_common.h"
+#include "kernel/hashlib.h"
 
+#include "libs/plf_colony/plf_colony.h"
 #include <cstdint>
 #include <limits>
 #include <span>
@@ -15,395 +17,408 @@
 
 YOSYS_NAMESPACE_BEGIN
 
-// A Twine is an interned, possibly composite source-location string. Leaves
-// are flat path:line.col substrings (the existing src-attribute literal). A
-// Concat node holds an ordered sequence of child twines, so merging the src
-// of N cells is O(N) lookups plus one concat-table probe — independent of
-// the total path-string length the materialized result would have.
-//
-// Twines are valid only relative to the TwinePool that minted them. The pool
-// lives on RTLIL::Design (design->twines).
-struct Twine
-{
-	using Id = Twine*;
-	static constexpr Id Null = nullptr;
+struct Twine;
+struct TwineRef {
+	std::variant<Twine*, size_t> data;
+	constexpr TwineRef(Twine* p) : data(p) {}
+	constexpr TwineRef(size_t global) : data(global) {}
+	const Twine& operator*() const;
+	Twine& operator*();
+	Twine* operator->() {
+		return &(**this);
+	}
+	const Twine* operator->() const {
+		return &(**this);
+	}
+	friend constexpr bool operator==(const TwineRef& a, const TwineRef& b) {
+		return &*a == &*b;
+	}
+	friend constexpr auto operator<=>(const TwineRef& a, const TwineRef& b) {
+		return &*a <=> &*b;
+	}
+};
+// using TwineRef = const Twine*;
+
+struct Twine {
+	static constexpr TwineRef Null = nullptr;
 
-	// Suffix shares a `prefix` prefix with other suffixes and contributes
-	// its own `tail` string. The materialized leaf string is
-	// flat_string(prefix) + tail, i.e. suffixes form trees whose leaves
-	// (string variant) are the roots — like a reverse-trie of common
-	// prefixes. The prefix is itself flat (Leaf or Suffix), never a
-	// Concat.
 	struct Suffix {
-		Id prefix;
+		TwineRef prefix;
 		std::string tail;
+		// TODO check
+		// auto operator<=>(const Suffix&) const = default;
 	};
 
-	// Leaf holds the literal path:line.col string. Suffix holds a prefix
-	// id + own tail (see above). Concat holds the ordered children.
-	// Concats are kept flat by TwinePool::concat — children are always
-	// flat (Leaf or Suffix), never other Concats. monostate is the
-	// tombstone marker for freed slots awaiting reuse via the free list.
-	std::variant<std::monostate, std::string, std::vector<Id>, Suffix> data;
+	std::variant<std::monostate, std::string, std::vector<TwineRef>, Suffix> data;
 
 	bool is_dead() const { return std::holds_alternative<std::monostate>(data); }
 	bool is_leaf() const { return std::holds_alternative<std::string>(data); }
-	bool is_concat() const { return std::holds_alternative<std::vector<Id>>(data); }
+	bool is_concat() const { return std::holds_alternative<std::vector<TwineRef>>(data); }
 	bool is_suffix() const { return std::holds_alternative<Suffix>(data); }
 	bool is_flat() const { return is_leaf() || is_suffix(); }
 	const std::string &leaf() const { return std::get<std::string>(data); }
-	const std::vector<Id> &children() const { return std::get<std::vector<Id>>(data); }
+	const std::vector<TwineRef> &children() const { return std::get<std::vector<TwineRef>>(data); }
 	const Suffix &suffix() const { return std::get<Suffix>(data); }
+	void dump(std::ostream& os = std::cout) const {
+		std::visit([&os](const auto& val) {
+			using T = std::decay_t<decltype(val)>;
+			if constexpr (std::is_same_v<T, std::monostate>) {
+				os << "Dead()";
+			} else if constexpr (std::is_same_v<T, std::string>) {
+				os << "Leaf(\"" << val << "\")";
+			} else if constexpr (std::is_same_v<T, std::vector<TwineRef>>) {
+				os << "Concat[";
+				for (size_t i = 0; i < val.size(); ++i) {
+					if (i > 0)
+						os << ", ";
+					val[i]->dump(os);
+				}
+				os << "]";
+			} else if constexpr (std::is_same_v<T, Suffix>) {
+				os << "Suffix(prefix: ";
+				val.prefix->dump(os);
+				os << ", tail: \"" << val.tail << "\")";
+			}
+		}, data);
+	}
+	void print(std::ostream& os = std::cout) const {
+		std::visit([&os](const auto& val) {
+			using T = std::decay_t<decltype(val)>;
+			if constexpr (std::is_same_v<T, std::monostate>) {
+			} else if constexpr (std::is_same_v<T, std::string>) {
+				os << val;
+			} else if constexpr (std::is_same_v<T, std::vector<TwineRef>>) {
+				for (size_t i = 0; i < val.size(); ++i) {
+					if (i > 0)
+						os << "|";
+					val[i]->print(os);
+				}
+			} else if constexpr (std::is_same_v<T, Suffix>) {
+				val.prefix->print(os);
+				os << val.tail;
+			}
+		}, data);
+	}
+	std::string str() const {
+		std::string str;
+		std::stringstream os(str);
+		print(os);
+		return str;
+	}
 };
 
-struct TwinePoolExtender;
-class TwinePool
-{
-private:
-	friend struct TwinePoolExtender;
-	uint32_t& refcount(Twine::Id id);
-public:
-	TwinePool();
-	// Custom copy: functor pointers must target the NEW pool's nodes_.
-	TwinePool(const TwinePool &other);
-	TwinePool &operator=(const TwinePool &other);
-	// Move is deleted; the intrusive functors hold `this`, so a move would
-	// silently leave them pointing at the old (now-empty) pool.
-	TwinePool(TwinePool &&) = delete;
-	TwinePool &operator=(TwinePool &&) = delete;
+struct TwineHash {
+	using is_transparent = void;
 
-	// Intern a leaf string. Returns the same Id for byte-equal inputs. The
-	// returned Id carries one reference for the caller — release it when
-	// you are done holding it. Empty input returns Twine::Null.
-	Twine::Id intern(std::string_view leaf);
+	size_t operator()(const Twine& t) const noexcept;
+	size_t operator()(TwineRef ptr) const noexcept;
+	// size_t operator()(std::string_view v) const noexcept;
+};
 
-	// Intern a Suffix node. The resulting flat string is
-	// flat_string(prefix) + tail. `prefix` must be a flat node (Leaf or
-	// Suffix) — pass Twine::Null with a non-empty `tail` to fall back to
-	// intern(tail). Suffixes with the same (prefix, tail) dedup. The
-	// returned Id carries one reference for the caller. Internally the
-	// new suffix retains a reference on `prefix`; releasing the suffix
-	// releases that internal prefix ref. Empty `tail` returns `prefix`
-	// (with +1 ref for the caller).
-	Twine::Id intern_suffix(Twine::Id prefix, std::string_view tail);
+struct TwineEq {
+	using is_transparent = void;
 
-	// Build a Concat node referencing `parts` in order. Concat children are
-	// always leaves (flat-leaf invariant): any Concat passed in `parts` has
-	// its leaves spliced in instead. Duplicate leaves and Twine::Null are
-	// dropped. If only one distinct leaf remains its Id is returned directly
-	// (no Concat node created). Concats with the same child sequence dedup.
-	// The returned Id carries one reference for the caller. Internally the
-	// concat retains each child it stores; releasing the concat releases
-	// those internal child references.
-	Twine::Id concat(std::span<const Twine::Id> parts);
-	Twine::Id concat(Twine::Id a, Twine::Id b);
+	bool operator()(TwineRef a, TwineRef b) const noexcept;
+	bool operator()(TwineRef a, const Twine& b) const noexcept;
+	bool operator()(const Twine& a, TwineRef b) const noexcept;
+	// bool operator()(TwineRef a, std::string_view b) const noexcept;
+	// bool operator()(std::string_view a, TwineRef b) const noexcept;
+};
 
-	// Non-interning lookup: return the Id of the leaf whose string equals
-	// `sv`, or Twine::Null if no such leaf exists. Does not allocate.
-	Twine::Id lookup(std::string_view sv) const;
+struct TwinePool {
+	static std::vector<Twine> globals_;
+	plf::colony<Twine> backing;
+	std::unordered_set<TwineRef, TwineHash, TwineEq> index;
 
-	// Refcount control. retain bumps; release decrements and, on reaching
-	// zero, marks the slot dead, drops it from the dedup indexes, releases
-	// any child refs the slot owned, and pushes the slot id onto the free
-	// list for reuse by the next intern/concat. Both no-op on Twine::Null.
+	TwinePool() {
+		for (Twine& t : globals_)
+			index.insert(&t);
+	}
 
-	size_t index(Twine* p) const;
-	void retain(Twine::Id id);
-	void release(Twine::Id id);
-	uint32_t refcount(Twine::Id id) const;
-	bool is_alive(Twine::Id id) const;
+	TwineRef find(Twine t) const {
+		if (auto it = index.find(t); it != index.end()) {
+			return *it;
+		}
+		return Twine::Null;
+	}
 
-	// Quick character queries on any flat node — avoids materializing the
-	// full string for the common `name[0] == '$'` / `.isPublic()` tests.
-	char first_char(Twine::Id id) const;
-	bool is_public(Twine::Id id) const { return first_char(id) == '\\'; }
+	TwineRef add(Twine t) {
+		if (auto it = index.find(t); it != index.end()) {
+			return *it;
+		}
 
-	// Materialize a Twine to the pipe-separated flat string used by the
-	// existing src attribute convention. Leaves visit in left-to-right DFS
-	// order; duplicate leaves are skipped to match `pool`-style semantics.
-	std::string flatten(Twine::Id id, char sep = '|') const;
+		auto colony_it = backing.insert(std::move(t));
+		TwineRef ptr = &(*colony_it);
+		index.insert(ptr);
+		return ptr;
+	}
 
-	// Materialize a flat node (Leaf or Suffix) to its single string. id
-	// must be a flat node (not a Concat) and not Twine::Null.
-	std::string flat_string(Twine::Id id) const { return flat_string_(id); }
+	void dump(std::ostream& os = std::cout) const {
+		os << "--- TwinePool Dump (" << backing.size() << " nodes) ---\n";
+		for (const auto& t : backing) {
+			os << static_cast<const void*>(&t) << " -> ";
+			t.dump(os);
+			os << '\n';
+		}
+		os << "--------------------------------\n";
+	}
+	// Silly compat
+	std::string flat_string(TwineRef t) const { return t->str(); }
+};
 
-	// Format an interned Id as the canonical src-attribute reference "@N".
-	// Twine::Null formats as the empty string.
-	std::string format_ref(Twine::Id id) const;
+inline size_t TwineHash::operator()(const Twine& t) const noexcept {
+	// size_t h = std::hash<size_t>{}(t.data.index());
+	Hasher h;
 
-	// Parse an "@N" reference back to an Id
-	static std::optional<size_t> parse_ref(std::string_view s);
-	Twine::Id get_ref(std::string_view s);
+	std::visit([&h](const auto& val) {
+		using T = std::decay_t<decltype(val)>;
 
-	const Twine &operator[](Twine::Id id) const { return *id; }
+		// auto combine = [&h](auto v) {
+		// 	h ^= v + 0x9e3779b9 + (h << 6) + (h >> 2); 
+		// };
 
-	size_t size() const { return nodes_.size(); }
-	size_t leaf_count() const { return leaf_index_.size(); }
-	size_t concat_count() const { return concat_index_.size(); }
-	size_t suffix_count() const { return suffix_index_.size(); }
+		if constexpr (std::is_same_v<T, std::string>) {
+			h.eat(val);
+			// combine(std::hash<std::string>{}(val));
+		} else if constexpr (std::is_same_v<T, std::vector<TwineRef>>) {
+			for (auto ref : val) {
+				h.eat(ref);
+				// combine(std::hash<TwineRef>{}(ref));
+			}
+		} else if constexpr (std::is_same_v<T, Twine::Suffix>) {
+			h.eat(val.prefix);
+			h.eat(val.tail);
+			// combine(std::hash<TwineRef>{}(val.prefix));
+			// combine(std::hash<std::string>{}(val.tail));
+		}
+	}, t.data);
 
-	// One-shot debug dump of the entire pool to stdout via log(). Each leaf
-	// shows its string; each concat shows its child id list. Intended for
-	// `dump -twines` or ad-hoc tracing — output volume scales with size().
-	void dump(const char *banner = nullptr) const;
+	return h.yield();
+}
 
-	// Rebuild the pool to contain only the nodes named in `live` plus the
-	// transitive children of any live concats. Returns an old-id -> new-id
-	// remap; ids not in the result are dead. Callers must rewrite every
-	// stored "@N" cell src through the returned remap immediately, since
-	// after this call the old ids no longer mean what they used to.
-	dict<Twine::Id, Twine::Id> gc(const pool<Twine::Id> &live);
+inline size_t TwineHash::operator()(TwineRef ptr) const noexcept {
+	return (*this)(*ptr);
+}
 
-	// Reconstruct `src->nodes_[src_id]` inside *this. Walks the structure
-	// — intern leaves, concat children — so a concat in `src` becomes a
-	// concat in this pool, not a flat literal of its leaves. Returns the
-	// id in this pool with +1 for the caller (release when done). Both
-	// pools may differ; the source is consulted read-only.
-	Twine::Id copy_from(const TwinePool &src, Twine::Id src_id);
+inline bool TwineEq::operator()(TwineRef a, TwineRef b) const noexcept {
+	return a->data == b->data;
+}
 
-	// Iterate every live (non-tombstoned) node. fn is `void(Twine::Id, const Twine&)`.
-	template <typename Fn>
-	void for_each_live(Fn fn) const {
-		for (auto& n : nodes_) {
-			if (n.is_dead())
-				continue;
-			fn(&n, n); // TODO de-stupid this
+inline bool TwineEq::operator()(TwineRef a, const Twine& b) const noexcept {
+	return a->data == b.data;
+}
+
+inline bool TwineEq::operator()(const Twine& a, TwineRef b) const noexcept {
+	return a.data == b->data;
+}
+
+
+struct DeepTwineHash {
+	using is_transparent = void;
+
+	// FNV-1a constants for 64-bit
+	static constexpr size_t FNV_OFFSET_BASIS = 14695981039346656037ull;
+	static constexpr size_t FNV_PRIME = 1099511628211ull;
+
+	static void combine(size_t& hash, std::string_view sv) noexcept {
+		for (char c : sv) {
+			hash ^= static_cast<size_t>(c);
+			hash *= FNV_PRIME;
 		}
 	}
 
-private:
-	std::vector<Twine> nodes_;
-	std::vector<uint32_t> refcount_;
-	std::list<Twine::Id> free_list_;
+	// Recursively hash the fragments of a Twine
+	static void combine(size_t& hash, TwineRef t) noexcept {
+		if (!t || t->is_dead()) return;
 
-	// --- Intrusive dedup indexes (Step 0) -----------------------------------
-	// Each set stores only the Twine::Id; hash/eq functors reach into
-	// nodes_[id] for the keying data. This avoids the duplicate-string cost
-	// of the old dict<std::string, Twine::Id> approach.
-	// All functors hold a raw pointer to *this; TwinePool is non-movable
-	// and copy-assignment rebuilds the sets from scratch so the pointer
-	// always stays valid.
+		if (t->is_leaf()) {
+			combine(hash, t->leaf());
+		} else if (t->is_concat()) {
+			for (auto child : t->children()) combine(hash, child);
+		} else if (t->is_suffix()) {
+			combine(hash, t->suffix().prefix);
+			combine(hash, t->suffix().tail);
+		}
+	}
 
-	using SuffixKey = std::pair<Twine::Id, std::string_view>;
+	size_t operator()(std::string_view sv) const noexcept {
+		size_t h = FNV_OFFSET_BASIS;
+		combine(h, sv);
+		return h;
+	}
 
-	struct LeafHash {
-		using is_transparent = void;
-		const TwinePool *pool;
-		size_t operator()(Twine::Id id) const noexcept {
-			return std::hash<std::string_view>{}(id->leaf());
-		}
-		size_t operator()(std::string_view sv) const noexcept {
-			return std::hash<std::string_view>{}(sv);
-		}
-	};
-	struct LeafEq {
-		using is_transparent = void;
-		const TwinePool *pool;
-		bool operator()(Twine::Id a, Twine::Id b) const noexcept {
-			return a->leaf() == b->leaf();
-		}
-		bool operator()(Twine::Id id, std::string_view sv) const noexcept {
-			return id->leaf() == sv;
-		}
-		bool operator()(std::string_view sv, Twine::Id id) const noexcept {
-			return sv == id->leaf();
-		}
-	};
-	struct SuffixHash {
-		using is_transparent = void;
-		const TwinePool *pool;
-		static size_t combine(size_t a, size_t b) noexcept {
-			return a ^ (b + 0x9e3779b9u + (a << 6) + (a >> 2));
-		}
-		size_t operator()(Twine::Id id) const noexcept {
-			const auto &s = id->suffix();
-			return combine(std::hash<Twine::Id>{}(s.prefix),
-			               std::hash<std::string_view>{}(s.tail));
-		}
-		size_t operator()(SuffixKey k) const noexcept {
-			return combine(std::hash<Twine::Id>{}(k.first),
-			               std::hash<std::string_view>{}(k.second));
-		}
-	};
-	struct SuffixEq {
-		using is_transparent = void;
-		const TwinePool *pool;
-		bool operator()(Twine::Id a, Twine::Id b) const noexcept {
-			const auto &sa = a->suffix();
-			const auto &sb = b->suffix();
-			return sa.prefix == sb.prefix && sa.tail == sb.tail;
-		}
-		bool operator()(Twine::Id id, SuffixKey k) const noexcept {
-			const auto &s = id->suffix();
-			return s.prefix == k.first && s.tail == k.second;
-		}
-		bool operator()(SuffixKey k, Twine::Id id) const noexcept {
-			return (*this)(id, k);
-		}
-	};
-	struct ConcatHash {
-		using is_transparent = void;
-		const TwinePool *pool;
-		static size_t hash_ids(std::span<const Twine::Id> v) noexcept {
-			size_t h = 0;
-			for (Twine::Id c : v)
-				h ^= std::hash<Twine::Id>{}(c) + 0x9e3779b9u + (h << 6) + (h >> 2);
-			return h;
-		}
-		size_t operator()(Twine::Id id) const noexcept {
-			return hash_ids(id->children());
-		}
-		size_t operator()(std::span<const Twine::Id> v) const noexcept {
-			return hash_ids(v);
-		}
-	};
-	struct ConcatEq {
-		using is_transparent = void;
-		const TwinePool *pool;
-		bool operator()(Twine::Id a, Twine::Id b) const noexcept {
-			return a->children() == b->children();
-		}
-		bool operator()(Twine::Id id, std::span<const Twine::Id> v) const noexcept {
-			const auto &ch = id->children();
-			return ch.size() == v.size() &&
-			       std::equal(ch.begin(), ch.end(), v.begin());
-		}
-		bool operator()(std::span<const Twine::Id> v, Twine::Id id) const noexcept {
-			return (*this)(id, v);
-		}
-	};
-
-	std::unordered_set<Twine::Id, LeafHash,   LeafEq>   leaf_index_;
-	std::unordered_set<Twine::Id, SuffixHash, SuffixEq> suffix_index_;
-	std::unordered_set<Twine::Id, ConcatHash, ConcatEq> concat_index_;
-	// -------------------------------------------------------------------------
-
-	Twine::Id alloc_slot_(Twine &&node);
-	void destroy_slot_(Twine::Id id);
-	void collect_leaves(Twine::Id id, pool<std::string> &out) const;
-	// Materialize a flat node (Leaf or Suffix) into its full string.
-	std::string flat_string_(Twine::Id id) const;
-	// Populate the three indexes from the current nodes_ vector (used by
-	// the copy constructor/assignment and by gc()).
-	void rebuild_indexes_();
+	size_t operator()(TwineRef t) const noexcept {
+		size_t h = FNV_OFFSET_BASIS;
+		combine(h, t);
+		return h;
+	}
 };
 
-// // Owning reference to a Twine slot. Retains on construction (and on copy
-// // of a non-empty ref), releases on destruction. Use this in transient
-// // container types — FfData, Mem helpers — that need to keep a src_id_
-// // alive across destruction of the original AttrObject that minted it,
-// // without having to fall back to a flattened path-string stash.
-// //
-// // Empty (no pool/no id) by default. A non-empty ref always carries a
-// // non-null pool and a live id.
-// class OwnedTwine
-// {
-// public:
-// 	OwnedTwine() = default;
+struct DeepTwineEq {
+	using is_transparent = void;
 
-// 	// Adopt the +1 reference returned by `intern` / `concat` / `intern_suffix`
-// 	// / `copy_from`. Use OwnedTwine(pool, id, retain=true) when copying an
-// 	// id already held elsewhere (e.g. another AttrObject's src_id_).
-// 	OwnedTwine(TwinePool *pool, Twine::Id id, bool retain = true) : pool_(pool), id_(id) {
-// 		if (retain && pool_ && id_ != Twine::Null)
-// 			pool_->retain(id_);
-// 	}
+	// Recursively consumes the string_view to check for deep equality
+	static bool consume(TwineRef t, std::string_view& sv) noexcept {
+		if (!t || t->is_dead()) return true;
 
-// 	OwnedTwine(const OwnedTwine &other) : pool_(other.pool_), id_(other.id_) {
-// 		if (pool_ && id_ != Twine::Null)
-// 			pool_->retain(id_);
-// 	}
+		if (t->is_leaf()) {
+			if (!sv.starts_with(t->leaf())) return false;
+			sv.remove_prefix(t->leaf().size());
+			return true;
+		} else if (t->is_concat()) {
+			for (auto child : t->children()) {
+				if (!consume(child, sv)) return false;
+			}
+			return true;
+		} else if (t->is_suffix()) {
+			if (!consume(t->suffix().prefix, sv)) return false;
+			if (!sv.starts_with(t->suffix().tail)) return false;
+			sv.remove_prefix(t->suffix().tail.size());
+			return true;
+		}
+		return false;
+	}
 
-// 	OwnedTwine(OwnedTwine &&other) noexcept : pool_(other.pool_), id_(other.id_) {
-// 		other.pool_ = nullptr;
-// 		other.id_ = Twine::Null;
-// 	}
+	bool operator()(TwineRef t, std::string_view sv) const noexcept {
+		return consume(t, sv) && sv.empty();
+	}
 
-// 	OwnedTwine &operator=(const OwnedTwine &other) {
-// 		if (this == &other)
-// 			return *this;
-// 		release_();
-// 		pool_ = other.pool_;
-// 		id_ = other.id_;
-// 		if (pool_ && id_ != Twine::Null)
-// 			pool_->retain(id_);
-// 		return *this;
-// 	}
+	bool operator()(std::string_view sv, TwineRef t) const noexcept {
+		return (*this)(t, sv);
+	}
 
-// 	OwnedTwine &operator=(OwnedTwine &&other) noexcept {
-// 		if (this == &other)
-// 			return *this;
-// 		release_();
-// 		pool_ = other.pool_;
-// 		id_ = other.id_;
-// 		other.pool_ = nullptr;
-// 		other.id_ = Twine::Null;
-// 		return *this;
-// 	}
+	// Required by unordered_set to handle hash collisions between two TwineRefs.
+	bool operator()(TwineRef a, TwineRef b) const {
+		if (a == b) return true; // Pointer or structural equality shortcut
+		return (*this)(a, flatten(b));
+	}
 
-// 	~OwnedTwine() { release_(); }
+	// Helper to flatten a twine (used only during rare hash collisions)
+	static std::string flatten(TwineRef t) {
+		std::string result;
+		auto append = [&result](auto& self, TwineRef node) -> void {
+			if (!node || node->is_dead()) return;
+			if (node->is_leaf()) result += node->leaf();
+			else if (node->is_concat()) {
+				for (auto child : node->children()) self(self, child);
+			} else if (node->is_suffix()) {
+				self(self, node->suffix().prefix);
+				result += node->suffix().tail;
+			}
+		};
+		append(append, t);
+		return result;
+	}
+};
 
-// 	void reset() {
-// 		release_();
-// 		pool_ = nullptr;
-// 		id_ = Twine::Null;
-// 	}
+struct TwineSearch {
+	std::unordered_set<TwineRef, DeepTwineHash, DeepTwineEq> index;
+	TwinePool* pool;
+	TwineSearch(TwinePool* pool) : pool(pool) {
+		for (auto& t : pool->backing) {
+			index.insert(&t);
+		}
+	}
+	TwineRef find(std::string_view sv) const {
+		if (auto it = index.find(sv); it != index.end()) {
+			return *it;
+		}
+		return Twine::Null;
+	}
+};
 
-// 	TwinePool *pool() const { return pool_; }
-// 	Twine::Id id() const { return id_; }
-// 	bool empty() const { return id_ == Twine::Null; }
-
-// private:
-// 	TwinePool *pool_ = nullptr;
-// 	Twine::Id id_ = Twine::Null;
-
-// 	void release_() {
-// 		if (pool_ && id_ != Twine::Null)
-// 			pool_->release(id_);
-// 	}
+// enum : short {
+// 	STATIC_ID_BEGIN = 0,
+// #define X(N) IDX_##N,
+// #include "kernel/constids.inc"
+// #undef X
+// 	STATIC_ID_END
 // };
 
-struct TwinePoolExtender {
-	TwinePool& pool;
-	size_t offset;
-private:
-	size_t resize_for_idx(size_t idx) {
-		auto real_idx = offset + idx;
-		pool.nodes_.resize(std::max(pool.nodes_.size(), real_idx + 1));
-		return real_idx;
-	}
-	void commit(Twine&& twine, size_t idx) {
-		pool.nodes_[idx] = std::move(twine);
-		pool.leaf_index_.insert(&pool.nodes_[idx]);
-	}
+
+class TW
+{
 public:
-	// TwinePoolExtender(Design* design) : pool(design->twines), offset(design->twines.size()) {}
-	void extend_leaf(std::string leaf, size_t idx) {
-		auto real_idx = resize_for_idx(idx);
-		commit(Twine(leaf), real_idx);
-	}
-	void extend_concat(std::vector<size_t> children, size_t idx) {
-		auto real_idx = resize_for_idx(idx);
-		Twine* first = &pool.nodes_.front() + offset;
-		std::vector<Twine*> real_children;
-		real_children.reserve(children.size());
-		for (auto child : children)
-			real_children.push_back(first + child);
-		commit(Twine(std::move(real_children)), real_idx);
-	}
-	void extend_suffix(size_t prefix, std::string tail, size_t idx) {
-		auto real_idx = resize_for_idx(idx);
-		Twine* first = &pool.nodes_.front() + offset;
-		Twine* real_prefix = first + prefix;
-		commit(Twine(Twine::Suffix(real_prefix, std::move(tail))), real_idx);
-	}
-	void finish() {
-		for (size_t i = offset; i < pool.nodes_.size(); i++)
-			if (pool.nodes_[i].is_dead())
-				pool.free_list_.push_back(&pool.nodes_[i]);
+	constexpr explicit TW(short v) : internal(v) {}
+
+	constexpr operator TwineRef() const
+	{
+		return &TwinePool::globals_[internal];
 	}
+
+#define X(N) static const TW N;
+#include "kernel/constids.inc"
+#undef X
+
+private:
+	short internal;
 };
 
+Twine& TwineRef::operator*() {
+	// Ugly
+	std::visit([](const auto& data) {
+		using T = std::decay_t<decltype(data)>;
+		if constexpr (std::is_same_v<Twine*, std::monostate>) {
+			return *data;
+		} else {
+			return TwinePool::globals_[data];
+		}
+	}, data);
+}
+
+const Twine& TwineRef::operator*() const {
+	// Ugly
+	std::visit([](const auto& data) {
+		using T = std::decay_t<decltype(data)>;
+		if constexpr (std::is_same_v<Twine*, std::monostate>) {
+			return *data;
+		} else {
+			return TwinePool::globals_[data];
+		}
+	}, data);
+}
+
+// struct TwinePoolExtender {
+// 	TwinePool& pool;
+// 	size_t offset;
+// private:
+// 	size_t resize_for_idx(size_t idx) {
+// 		auto real_idx = offset + idx;
+// 		pool.nodes_.resize(std::max(pool.nodes_.size(), real_idx + 1));
+// 		return real_idx;
+// 	}
+// 	void commit(Twine&& twine, size_t idx) {
+// 		pool.nodes_[idx] = std::move(twine);
+// 		pool.leaf_index_.insert(&pool.nodes_[idx]);
+// 	}
+// public:
+// 	// TwinePoolExtender(Design* design) : pool(design->twines), offset(design->twines.size()) {}
+// 	void extend_leaf(std::string leaf, size_t idx) {
+// 		auto real_idx = resize_for_idx(idx);
+// 		commit(Twine(leaf), real_idx);
+// 	}
+// 	void extend_concat(std::vector<size_t> children, size_t idx) {
+// 		auto real_idx = resize_for_idx(idx);
+// 		Twine* first = &pool.nodes_.front() + offset;
+// 		std::vector<Twine*> real_children;
+// 		real_children.reserve(children.size());
+// 		for (auto child : children)
+// 			real_children.push_back(first + child);
+// 		commit(Twine(std::move(real_children)), real_idx);
+// 	}
+// 	void extend_suffix(size_t prefix, std::string tail, size_t idx) {
+// 		auto real_idx = resize_for_idx(idx);
+// 		Twine* first = &pool.nodes_.front() + offset;
+// 		Twine* real_prefix = first + prefix;
+// 		commit(Twine(Twine::Suffix(real_prefix, std::move(tail))), real_idx);
+// 	}
+// 	void finish() {
+// 		for (size_t i = offset; i < pool.nodes_.size(); i++)
+// 			if (pool.nodes_[i].is_dead())
+// 				pool.free_list_.push_back(&pool.nodes_[i]);
+// 	}
+// };
+
 YOSYS_NAMESPACE_END
 
 #endif
diff --git a/kernel/unstable/patch.cc b/kernel/unstable/patch.cc
index 0ad08ea2b..1f669a889 100644
--- a/kernel/unstable/patch.cc
+++ b/kernel/unstable/patch.cc
@@ -50,7 +50,7 @@ Wire* Patch::commit_wire(std::unique_ptr<Wire> wire) {
 	Wire* raw = wire.release();
 	IdString name = staged_wire_names_.at(raw);
 	staged_wire_names_.erase(raw);
-	Twine::Id id = mod->design->twines.intern(name.str());
+	TwineRef id = mod->design->twines.intern(name.str());
 	mod->design->obj_set_name_id(raw, id);
 	mod->design->twines.release(id);
 	mod->wires_[raw->meta_->name_id] = raw;
@@ -62,7 +62,7 @@ Cell* Patch::commit_cell(std::unique_ptr<Cell> cell) {
 	Cell* raw = cell.release();
 	IdString name = staged_cell_names_.at(raw);
 	staged_cell_names_.erase(raw);
-	Twine::Id id = mod->design->twines.intern(name.str());
+	TwineRef id = mod->design->twines.intern(name.str());
 	mod->design->obj_set_name_id(raw, id);
 	mod->design->twines.release(id);
 	raw->module = mod;
@@ -95,7 +95,7 @@ namespace {
 			return;
 
 		TwinePool& pool = mod->design->twines;
-		std::vector<Twine::Id> ids;
+		std::vector<TwineRef> ids;
 		ids.reserve(2 + extras.size());
 		auto push = [&](Cell *c) {
 			if (c && c->src_id() != Twine::Null)
@@ -107,7 +107,7 @@ namespace {
 		push(merge_src_into);
 		if (ids.empty())
 			return;
-		Twine::Id merged = pool.concat(std::span<const Twine::Id>{ids});
+		TwineRef merged = pool.concat(std::span<const TwineRef>{ids});
 		if (ys_debug()) {
 			log_debug("twine: merge yields %s (pool size %zu)\n",
 					pool.format_ref(merged).c_str(), pool.size());
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index d4bdd0922..b608a482b 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -240,6 +240,7 @@ void yosys_setup()
 	already_shutdown = false;
 
 	IdString::ensure_prepopulated();
+	Twine::ensure_prepopulated();
 
 #ifdef YOSYS_ENABLE_PYTHON
 	// Starting Python 3.12, calling PyImport_AppendInittab on an already
diff --git a/libs/plf_colony b/libs/plf_colony
new file mode 160000
index 000000000..bc11fa510
--- /dev/null
+++ b/libs/plf_colony
@@ -0,0 +1 @@
+Subproject commit bc11fa510423f80308fa43818185df01f41a29c8
diff --git a/passes/cmds/dump_twines.cc b/passes/cmds/dump_twines.cc
index a067f3c02..1c9b26e22 100644
--- a/passes/cmds/dump_twines.cc
+++ b/passes/cmds/dump_twines.cc
@@ -42,7 +42,7 @@ struct DumpTwinesPass : public Pass {
 		const TwinePool &pool = design->twines;
 		log("twine pool: %zu nodes (%zu leaves, %zu suffixes, %zu concats)\n",
 				pool.size(), pool.leaf_count(), pool.suffix_count(), pool.concat_count());
-		pool.for_each_live([&](Twine::Id id, const Twine &n) {
+		pool.for_each_live([&](TwineRef id, const Twine &n) {
 			if (n.is_leaf()) {
 				log("  @%u leaf rc=%u %s\n", id, pool.refcount(id), n.leaf().c_str());
 			} else if (n.is_suffix()) {
@@ -56,7 +56,7 @@ struct DumpTwinesPass : public Pass {
 				}
 			} else {
 				std::string children;
-				for (Twine::Id c : n.children()) {
+				for (TwineRef c : n.children()) {
 					if (!children.empty())
 						children += ", ";
 					children += "@" + std::to_string(c);
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index d96f3803a..04299d570 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -117,7 +117,7 @@ struct MemoryMapWorker
 		// new cell. set_src_attribute's parse_ref path retains the
 		// pool slot directly.
 		{
-			Twine::Id mid = (mem.module && mem.module->design) ? mem.module->design->obj_src_id(&mem) : Twine::Null;
+			TwineRef mid = (mem.module && mem.module->design) ? mem.module->design->obj_src_id(&mem) : Twine::Null;
 			mem_src = (mid != Twine::Null) ? TwinePool::format_ref(mid) : std::string();
 		}
 
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index d4de4afde..c16cefa98 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -479,7 +479,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 	if (!noclkinv)
 	for (auto cell : dirty_cells)
-	if (design->selected(module, cell)) {
+	if (design->selected_member(module, cell)) {
 		if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2)))
 			handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map);
 
diff --git a/passes/tests/raise_error.cc b/passes/tests/raise_error.cc
index 95b477bc8..0a75f4d0e 100644
--- a/passes/tests/raise_error.cc
+++ b/passes/tests/raise_error.cc
@@ -1,3 +1,4 @@
+#include "kernel/rtlil.h"
 #include "kernel/yosys.h"
 
 USING_YOSYS_NAMESPACE
@@ -46,7 +47,7 @@ struct RaiseErrorPass : public Pass {
 
 		extra_args(args, argidx, design, true);
 
-		RTLIL::NamedObject *err_obj = nullptr;
+		RTLIL::AttrObject *err_obj = nullptr;
 
 		for (auto mod : design->all_selected_modules()) {
 			if (mod->has_attribute(ID::raise_error)) {