Move presentation intro example

Rework images makefile a bit to get it to import and build from resources folder(s).
Currently requires running twice from a clean build due to the way it finds `.dot` files to convert.

docs/resources/PRESENTATION_Intro/.gitignore

@@ -0,0 +1,8 @@
+counter_00.dot
+counter_01.dot
+counter_02.dot
+counter_03.dot
+counter_00.pdf
+counter_01.pdf
+counter_02.pdf
+counter_03.pdf

docs/resources/PRESENTATION_Intro/Makefile

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+
+all: counter_00.dot counter_01.dot counter_02.dot counter_03.dot
+
+counter_00.dot: counter.v counter.ys mycells.lib
+	../../../yosys counter_outputs.ys
+
+counter_01.dot: counter_00.dot
+counter_02.dot: counter_00.dot
+counter_03.dot: counter_00.dot
+

docs/resources/PRESENTATION_Intro/counter.v

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+module counter (clk, rst, en, count);
+
+	input clk, rst, en;
+	output reg [1:0] count;
+
+	always @(posedge clk)
+		if (rst)
+			count <= 2'd0;
+		else if (en)
+			count <= count + 2'd1;
+
+endmodule

docs/resources/PRESENTATION_Intro/counter.ys

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+# read design
+read_verilog counter.v
+hierarchy -check -top counter
+
+# the high-level stuff
+proc; opt; memory; opt; fsm; opt
+
+# mapping to internal cell library
+techmap; opt
+
+# mapping flip-flops to mycells.lib
+dfflibmap -liberty mycells.lib
+
+# mapping logic to mycells.lib
+abc -liberty mycells.lib
+
+# cleanup
+clean
+
+# write synthesized design
+write_verilog synth.v

docs/resources/PRESENTATION_Intro/counter_outputs.ys

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+# read design
+read_verilog counter.v
+hierarchy -check -top counter
+
+show -notitle -format dot -prefix counter_00
+
+# the high-level stuff
+proc; opt; memory; opt; fsm; opt
+
+show -notitle -format dot -prefix counter_01
+
+# mapping to internal cell library
+techmap; opt
+
+splitnets -ports;;
+show -notitle -format dot -prefix counter_02
+
+# mapping flip-flops to mycells.lib
+dfflibmap -liberty mycells.lib
+
+# mapping logic to mycells.lib
+abc -liberty mycells.lib
+
+# cleanup
+clean
+
+show -notitle -lib mycells.v -format dot -prefix counter_03

docs/resources/PRESENTATION_Intro/mycells.lib

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+library(demo) {
+  cell(BUF) {
+    area: 6;
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "A"; }
+  }
+  cell(NOT) {
+    area: 3;
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "A'"; }
+  }
+  cell(NAND) {
+    area: 4;
+    pin(A) { direction: input; }
+    pin(B) { direction: input; }
+    pin(Y) { direction: output;
+             function: "(A*B)'"; }
+  }
+  cell(NOR) {
+    area: 4;
+    pin(A) { direction: input; }
+    pin(B) { direction: input; }
+    pin(Y) { direction: output;
+             function: "(A+B)'"; }
+  }
+  cell(DFF) {
+    area: 18;
+    ff(IQ, IQN) { clocked_on: C;
+                  next_state: D; }
+    pin(C) { direction: input;
+                 clock: true; }
+    pin(D) { direction: input; }
+    pin(Q) { direction: output;
+              function: "IQ"; }
+  }
+}

docs/resources/PRESENTATION_Intro/mycells.v

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+
+module NOT(A, Y);
+input A;
+output Y = ~A;
+endmodule
+
+module NAND(A, B, Y);
+input A, B;
+output Y = ~(A & B);
+endmodule
+
+module NOR(A, B, Y);
+input A, B;
+output Y = ~(A | B);
+endmodule
+
+module DFF(C, D, Q);
+input C, D;
+output reg Q;
+always @(posedge C)
+	Q <= D;
+endmodule
+