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https://github.com/YosysHQ/yosys
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20c2708383
Rework images makefile a bit to get it to import and build from resources folder(s). Currently requires running twice from a clean build due to the way it finds `.dot` files to convert.
24 lines
272 B
Verilog
24 lines
272 B
Verilog
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module NOT(A, Y);
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input A;
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output Y = ~A;
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endmodule
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module NAND(A, B, Y);
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input A, B;
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output Y = ~(A & B);
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endmodule
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module NOR(A, B, Y);
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input A, B;
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output Y = ~(A | B);
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endmodule
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module DFF(C, D, Q);
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input C, D;
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output reg Q;
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always @(posedge C)
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Q <= D;
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endmodule
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