mirror of
https://github.com/YosysHQ/yosys
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Delete synth_ecp5
This commit is contained in:
Miodrag Milanovic
parent
4a0d1121ea
commit
0da1ab0cbd
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@ -1,15 +0,0 @@
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OBJS += techlibs/ecp5/synth_ecp5.o
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_ff.vh))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_io.vh))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams_map.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams.txt))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams.txt))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
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@ -1,90 +0,0 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2018 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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(* techmap_celltype = "$alu" *)
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module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y;
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input CI, BI;
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(* force_downto *)
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output [Y_WIDTH-1:0] CO;
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wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
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(* force_downto *)
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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function integer round_up2;
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input integer N;
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begin
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round_up2 = ((N + 1) / 2) * 2;
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end
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endfunction
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localparam Y_WIDTH2 = round_up2(Y_WIDTH);
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(* force_downto *)
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wire [Y_WIDTH2-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
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(* force_downto *)
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wire [Y_WIDTH2-1:0] BX = B_buf;
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(* force_downto *)
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wire [Y_WIDTH2-1:0] C = {CO, CI};
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(* force_downto *)
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wire [Y_WIDTH2-1:0] FCO, Y1;
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genvar i;
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generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
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CCU2C #(
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.INIT0(16'b1001011010101010),
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.INIT1(16'b1001011010101010),
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.INJECT1_0("NO"),
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.INJECT1_1("NO")
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) ccu2c_i (
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.CIN(C[i]),
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.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1),
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.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1),
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.S0(Y[i]), .S1(Y1[i]),
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.COUT(FCO[i])
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);
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assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
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if (i+1 < Y_WIDTH) begin
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assign CO[i+1] = FCO[i];
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assign Y[i+1] = Y1[i];
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end
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end endgenerate
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assign X = AA ^ BB;
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endmodule
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@ -1,52 +0,0 @@
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ram block $__ECP5_DP16KD_ {
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abits 14;
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widths 1 2 4 9 18 per_port;
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byte 9;
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cost 128;
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init no_undef;
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port srsw "A" "B" {
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clock anyedge;
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clken;
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wrbe_separate;
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portoption "WRITEMODE" "NORMAL" {
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rdwr no_change;
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}
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portoption "WRITEMODE" "WRITETHROUGH" {
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rdwr new;
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}
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portoption "WRITEMODE" "READBEFOREWRITE" {
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rdwr old;
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}
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option "RESETMODE" "SYNC" {
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rdsrst zero ungated block_wr;
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}
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option "RESETMODE" "ASYNC" {
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rdarst zero;
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}
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rdinit zero;
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}
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}
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ram block $__ECP5_PDPW16KD_ {
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abits 14;
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widths 1 2 4 9 18 36 per_port;
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byte 9;
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cost 128;
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init no_undef;
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port sr "R" {
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clock anyedge;
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clken;
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option "RESETMODE" "SYNC" {
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rdsrst zero ungated;
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}
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option "RESETMODE" "ASYNC" {
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rdarst zero;
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}
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rdinit zero;
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}
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port sw "W" {
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width 36;
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clock anyedge;
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clken;
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}
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}
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@ -1,489 +0,0 @@
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module $__ECP5_DP16KD_ (...);
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parameter INIT = 0;
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parameter OPTION_RESETMODE = "SYNC";
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parameter PORT_A_WIDTH = 18;
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parameter PORT_A_WR_BE_WIDTH = 2;
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parameter PORT_A_CLK_POL = 1;
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parameter PORT_A_OPTION_WRITEMODE = "NORMAL";
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input PORT_A_WR_EN;
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input PORT_A_RD_SRST;
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input PORT_A_RD_ARST;
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input [13:0] PORT_A_ADDR;
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input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
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input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
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output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
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parameter PORT_B_WIDTH = 18;
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parameter PORT_B_WR_BE_WIDTH = 2;
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parameter PORT_B_CLK_POL = 1;
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parameter PORT_B_OPTION_WRITEMODE = "NORMAL";
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input PORT_B_CLK;
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input PORT_B_CLK_EN;
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input PORT_B_WR_EN;
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input PORT_B_RD_SRST;
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input PORT_B_RD_ARST;
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input [13:0] PORT_B_ADDR;
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input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE;
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input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
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output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
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function [319:0] init_slice;
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input integer idx;
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integer i, j;
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init_slice = 0;
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for (i = 0; i < 16; i = i + 1) begin
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init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];
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end
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endfunction
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wire [17:0] DOA;
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wire [17:0] DOB;
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wire [17:0] DIA = PORT_A_WR_DATA;
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wire [17:0] DIB = PORT_B_WR_DATA;
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assign PORT_A_RD_DATA = DOA;
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assign PORT_B_RD_DATA = DOB;
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DP16KD #(
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.INITVAL_00(init_slice('h00)),
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.INITVAL_01(init_slice('h01)),
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.INITVAL_02(init_slice('h02)),
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.INITVAL_03(init_slice('h03)),
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.INITVAL_04(init_slice('h04)),
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.INITVAL_05(init_slice('h05)),
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.INITVAL_06(init_slice('h06)),
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.INITVAL_07(init_slice('h07)),
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.INITVAL_08(init_slice('h08)),
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.INITVAL_09(init_slice('h09)),
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.INITVAL_0A(init_slice('h0a)),
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.INITVAL_0B(init_slice('h0b)),
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.INITVAL_0C(init_slice('h0c)),
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.INITVAL_0D(init_slice('h0d)),
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.INITVAL_0E(init_slice('h0e)),
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.INITVAL_0F(init_slice('h0f)),
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.INITVAL_10(init_slice('h10)),
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.INITVAL_11(init_slice('h11)),
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.INITVAL_12(init_slice('h12)),
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.INITVAL_13(init_slice('h13)),
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.INITVAL_14(init_slice('h14)),
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.INITVAL_15(init_slice('h15)),
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.INITVAL_16(init_slice('h16)),
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.INITVAL_17(init_slice('h17)),
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.INITVAL_18(init_slice('h18)),
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.INITVAL_19(init_slice('h19)),
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.INITVAL_1A(init_slice('h1a)),
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.INITVAL_1B(init_slice('h1b)),
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.INITVAL_1C(init_slice('h1c)),
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.INITVAL_1D(init_slice('h1d)),
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.INITVAL_1E(init_slice('h1e)),
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.INITVAL_1F(init_slice('h1f)),
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.INITVAL_20(init_slice('h20)),
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.INITVAL_21(init_slice('h21)),
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.INITVAL_22(init_slice('h22)),
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.INITVAL_23(init_slice('h23)),
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.INITVAL_24(init_slice('h24)),
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.INITVAL_25(init_slice('h25)),
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.INITVAL_26(init_slice('h26)),
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.INITVAL_27(init_slice('h27)),
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.INITVAL_28(init_slice('h28)),
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.INITVAL_29(init_slice('h29)),
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.INITVAL_2A(init_slice('h2a)),
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.INITVAL_2B(init_slice('h2b)),
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.INITVAL_2C(init_slice('h2c)),
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.INITVAL_2D(init_slice('h2d)),
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.INITVAL_2E(init_slice('h2e)),
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.INITVAL_2F(init_slice('h2f)),
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.INITVAL_30(init_slice('h30)),
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.INITVAL_31(init_slice('h31)),
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.INITVAL_32(init_slice('h32)),
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.INITVAL_33(init_slice('h33)),
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.INITVAL_34(init_slice('h34)),
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.INITVAL_35(init_slice('h35)),
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.INITVAL_36(init_slice('h36)),
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.INITVAL_37(init_slice('h37)),
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.INITVAL_38(init_slice('h38)),
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.INITVAL_39(init_slice('h39)),
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.INITVAL_3A(init_slice('h3a)),
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.INITVAL_3B(init_slice('h3b)),
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.INITVAL_3C(init_slice('h3c)),
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.INITVAL_3D(init_slice('h3d)),
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.INITVAL_3E(init_slice('h3e)),
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.INITVAL_3F(init_slice('h3f)),
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.DATA_WIDTH_A(PORT_A_WIDTH),
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.DATA_WIDTH_B(PORT_B_WIDTH),
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.REGMODE_A("NOREG"),
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.REGMODE_B("NOREG"),
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.RESETMODE(OPTION_RESETMODE),
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.ASYNC_RESET_RELEASE(OPTION_RESETMODE),
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.CSDECODE_A("0b000"),
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.CSDECODE_B("0b000"),
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.CLKAMUX(PORT_A_CLK_POL ? "CLKA" : "INV"),
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.CLKBMUX(PORT_B_CLK_POL ? "CLKB" : "INV"),
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.WRITEMODE_A(PORT_A_OPTION_WRITEMODE),
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.WRITEMODE_B(PORT_B_OPTION_WRITEMODE),
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.GSR("AUTO")
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) _TECHMAP_REPLACE_ (
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.CLKA(PORT_A_CLK),
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.WEA(PORT_A_WIDTH == 18 ? PORT_A_WR_EN : (PORT_A_WR_EN | PORT_A_WR_BE[0])),
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.CEA(PORT_A_CLK_EN),
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.OCEA(1'b1),
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.RSTA(OPTION_RESETMODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST),
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.CSA0(1'b0),
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.CSA1(1'b0),
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.CSA2(1'b0),
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.ADA0(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[0] : PORT_A_ADDR[0]),
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.ADA1(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[1] : PORT_A_ADDR[1]),
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.ADA2(PORT_A_ADDR[2]),
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.ADA3(PORT_A_ADDR[3]),
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.ADA4(PORT_A_ADDR[4]),
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.ADA5(PORT_A_ADDR[5]),
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.ADA6(PORT_A_ADDR[6]),
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.ADA7(PORT_A_ADDR[7]),
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.ADA8(PORT_A_ADDR[8]),
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.ADA9(PORT_A_ADDR[9]),
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.ADA10(PORT_A_ADDR[10]),
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.ADA11(PORT_A_ADDR[11]),
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.ADA12(PORT_A_ADDR[12]),
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.ADA13(PORT_A_ADDR[13]),
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.DIA0(DIA[0]),
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.DIA1(DIA[1]),
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.DIA2(DIA[2]),
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.DIA3(DIA[3]),
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.DIA4(DIA[4]),
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.DIA5(DIA[5]),
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.DIA6(DIA[6]),
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.DIA7(DIA[7]),
|
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.DIA8(DIA[8]),
|
||||
.DIA9(DIA[9]),
|
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.DIA10(DIA[10]),
|
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.DIA11(DIA[11]),
|
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.DIA12(DIA[12]),
|
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.DIA13(DIA[13]),
|
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.DIA14(DIA[14]),
|
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.DIA15(DIA[15]),
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.DIA16(DIA[16]),
|
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.DIA17(DIA[17]),
|
||||
.DOA0(DOA[0]),
|
||||
.DOA1(DOA[1]),
|
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.DOA2(DOA[2]),
|
||||
.DOA3(DOA[3]),
|
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.DOA4(DOA[4]),
|
||||
.DOA5(DOA[5]),
|
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.DOA6(DOA[6]),
|
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.DOA7(DOA[7]),
|
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.DOA8(DOA[8]),
|
||||
.DOA9(DOA[9]),
|
||||
.DOA10(DOA[10]),
|
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.DOA11(DOA[11]),
|
||||
.DOA12(DOA[12]),
|
||||
.DOA13(DOA[13]),
|
||||
.DOA14(DOA[14]),
|
||||
.DOA15(DOA[15]),
|
||||
.DOA16(DOA[16]),
|
||||
.DOA17(DOA[17]),
|
||||
|
||||
.CLKB(PORT_B_CLK),
|
||||
.WEB(PORT_B_WIDTH == 18 ? PORT_B_WR_EN : (PORT_B_WR_EN | PORT_B_WR_BE[0])),
|
||||
.CEB(PORT_B_CLK_EN),
|
||||
.OCEB(1'b1),
|
||||
.RSTB(OPTION_RESETMODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST),
|
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.CSB0(1'b0),
|
||||
.CSB1(1'b0),
|
||||
.CSB2(1'b0),
|
||||
.ADB0(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[0] : PORT_B_ADDR[0]),
|
||||
.ADB1(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[1] : PORT_B_ADDR[1]),
|
||||
.ADB2(PORT_B_ADDR[2]),
|
||||
.ADB3(PORT_B_ADDR[3]),
|
||||
.ADB4(PORT_B_ADDR[4]),
|
||||
.ADB5(PORT_B_ADDR[5]),
|
||||
.ADB6(PORT_B_ADDR[6]),
|
||||
.ADB7(PORT_B_ADDR[7]),
|
||||
.ADB8(PORT_B_ADDR[8]),
|
||||
.ADB9(PORT_B_ADDR[9]),
|
||||
.ADB10(PORT_B_ADDR[10]),
|
||||
.ADB11(PORT_B_ADDR[11]),
|
||||
.ADB12(PORT_B_ADDR[12]),
|
||||
.ADB13(PORT_B_ADDR[13]),
|
||||
.DIB0(DIB[0]),
|
||||
.DIB1(DIB[1]),
|
||||
.DIB2(DIB[2]),
|
||||
.DIB3(DIB[3]),
|
||||
.DIB4(DIB[4]),
|
||||
.DIB5(DIB[5]),
|
||||
.DIB6(DIB[6]),
|
||||
.DIB7(DIB[7]),
|
||||
.DIB8(DIB[8]),
|
||||
.DIB9(DIB[9]),
|
||||
.DIB10(DIB[10]),
|
||||
.DIB11(DIB[11]),
|
||||
.DIB12(DIB[12]),
|
||||
.DIB13(DIB[13]),
|
||||
.DIB14(DIB[14]),
|
||||
.DIB15(DIB[15]),
|
||||
.DIB16(DIB[16]),
|
||||
.DIB17(DIB[17]),
|
||||
.DOB0(DOB[0]),
|
||||
.DOB1(DOB[1]),
|
||||
.DOB2(DOB[2]),
|
||||
.DOB3(DOB[3]),
|
||||
.DOB4(DOB[4]),
|
||||
.DOB5(DOB[5]),
|
||||
.DOB6(DOB[6]),
|
||||
.DOB7(DOB[7]),
|
||||
.DOB8(DOB[8]),
|
||||
.DOB9(DOB[9]),
|
||||
.DOB10(DOB[10]),
|
||||
.DOB11(DOB[11]),
|
||||
.DOB12(DOB[12]),
|
||||
.DOB13(DOB[13]),
|
||||
.DOB14(DOB[14]),
|
||||
.DOB15(DOB[15]),
|
||||
.DOB16(DOB[16]),
|
||||
.DOB17(DOB[17]),
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module $__ECP5_PDPW16KD_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_RESETMODE = "SYNC";
|
||||
|
||||
parameter PORT_R_WIDTH = 36;
|
||||
parameter PORT_R_CLK_POL = 1;
|
||||
|
||||
input PORT_R_CLK;
|
||||
input PORT_R_CLK_EN;
|
||||
input PORT_R_RD_SRST;
|
||||
input PORT_R_RD_ARST;
|
||||
input [13:0] PORT_R_ADDR;
|
||||
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
|
||||
|
||||
parameter PORT_W_WIDTH = 36;
|
||||
parameter PORT_W_WR_EN_WIDTH = 4;
|
||||
parameter PORT_W_CLK_POL = 1;
|
||||
|
||||
input PORT_W_CLK;
|
||||
input PORT_W_CLK_EN;
|
||||
input [13:0] PORT_W_ADDR;
|
||||
input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
|
||||
input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
|
||||
|
||||
function [319:0] init_slice;
|
||||
input integer idx;
|
||||
integer i, j;
|
||||
init_slice = 0;
|
||||
for (i = 0; i < 16; i = i + 1) begin
|
||||
init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];
|
||||
end
|
||||
endfunction
|
||||
|
||||
wire [35:0] DI = PORT_W_WR_DATA;
|
||||
wire [35:0] DO;
|
||||
|
||||
assign PORT_R_RD_DATA = PORT_R_WIDTH == 36 ? DO : DO[35:18];
|
||||
|
||||
DP16KD #(
|
||||
.INITVAL_00(init_slice('h00)),
|
||||
.INITVAL_01(init_slice('h01)),
|
||||
.INITVAL_02(init_slice('h02)),
|
||||
.INITVAL_03(init_slice('h03)),
|
||||
.INITVAL_04(init_slice('h04)),
|
||||
.INITVAL_05(init_slice('h05)),
|
||||
.INITVAL_06(init_slice('h06)),
|
||||
.INITVAL_07(init_slice('h07)),
|
||||
.INITVAL_08(init_slice('h08)),
|
||||
.INITVAL_09(init_slice('h09)),
|
||||
.INITVAL_0A(init_slice('h0a)),
|
||||
.INITVAL_0B(init_slice('h0b)),
|
||||
.INITVAL_0C(init_slice('h0c)),
|
||||
.INITVAL_0D(init_slice('h0d)),
|
||||
.INITVAL_0E(init_slice('h0e)),
|
||||
.INITVAL_0F(init_slice('h0f)),
|
||||
.INITVAL_10(init_slice('h10)),
|
||||
.INITVAL_11(init_slice('h11)),
|
||||
.INITVAL_12(init_slice('h12)),
|
||||
.INITVAL_13(init_slice('h13)),
|
||||
.INITVAL_14(init_slice('h14)),
|
||||
.INITVAL_15(init_slice('h15)),
|
||||
.INITVAL_16(init_slice('h16)),
|
||||
.INITVAL_17(init_slice('h17)),
|
||||
.INITVAL_18(init_slice('h18)),
|
||||
.INITVAL_19(init_slice('h19)),
|
||||
.INITVAL_1A(init_slice('h1a)),
|
||||
.INITVAL_1B(init_slice('h1b)),
|
||||
.INITVAL_1C(init_slice('h1c)),
|
||||
.INITVAL_1D(init_slice('h1d)),
|
||||
.INITVAL_1E(init_slice('h1e)),
|
||||
.INITVAL_1F(init_slice('h1f)),
|
||||
.INITVAL_20(init_slice('h20)),
|
||||
.INITVAL_21(init_slice('h21)),
|
||||
.INITVAL_22(init_slice('h22)),
|
||||
.INITVAL_23(init_slice('h23)),
|
||||
.INITVAL_24(init_slice('h24)),
|
||||
.INITVAL_25(init_slice('h25)),
|
||||
.INITVAL_26(init_slice('h26)),
|
||||
.INITVAL_27(init_slice('h27)),
|
||||
.INITVAL_28(init_slice('h28)),
|
||||
.INITVAL_29(init_slice('h29)),
|
||||
.INITVAL_2A(init_slice('h2a)),
|
||||
.INITVAL_2B(init_slice('h2b)),
|
||||
.INITVAL_2C(init_slice('h2c)),
|
||||
.INITVAL_2D(init_slice('h2d)),
|
||||
.INITVAL_2E(init_slice('h2e)),
|
||||
.INITVAL_2F(init_slice('h2f)),
|
||||
.INITVAL_30(init_slice('h30)),
|
||||
.INITVAL_31(init_slice('h31)),
|
||||
.INITVAL_32(init_slice('h32)),
|
||||
.INITVAL_33(init_slice('h33)),
|
||||
.INITVAL_34(init_slice('h34)),
|
||||
.INITVAL_35(init_slice('h35)),
|
||||
.INITVAL_36(init_slice('h36)),
|
||||
.INITVAL_37(init_slice('h37)),
|
||||
.INITVAL_38(init_slice('h38)),
|
||||
.INITVAL_39(init_slice('h39)),
|
||||
.INITVAL_3A(init_slice('h3a)),
|
||||
.INITVAL_3B(init_slice('h3b)),
|
||||
.INITVAL_3C(init_slice('h3c)),
|
||||
.INITVAL_3D(init_slice('h3d)),
|
||||
.INITVAL_3E(init_slice('h3e)),
|
||||
.INITVAL_3F(init_slice('h3f)),
|
||||
.DATA_WIDTH_A(PORT_W_WIDTH),
|
||||
.DATA_WIDTH_B(PORT_R_WIDTH),
|
||||
.REGMODE_A("NOREG"),
|
||||
.REGMODE_B("NOREG"),
|
||||
.RESETMODE(OPTION_RESETMODE),
|
||||
.ASYNC_RESET_RELEASE(OPTION_RESETMODE),
|
||||
.CSDECODE_A("0b000"),
|
||||
.CSDECODE_B("0b000"),
|
||||
.CLKAMUX(PORT_W_CLK_POL ? "CLKA" : "INV"),
|
||||
.CLKBMUX(PORT_R_CLK_POL ? "CLKB" : "INV"),
|
||||
.GSR("AUTO")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.CLKA(PORT_W_CLK),
|
||||
.WEA(PORT_W_WIDTH >= 18 ? 1'b1 : PORT_W_WR_EN[0]),
|
||||
.CEA(PORT_W_CLK_EN),
|
||||
.OCEA(1'b0),
|
||||
.RSTA(1'b0),
|
||||
.CSA0(1'b0),
|
||||
.CSA1(1'b0),
|
||||
.CSA2(1'b0),
|
||||
.ADA0(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[0] : PORT_W_ADDR[0]),
|
||||
.ADA1(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[1] : PORT_W_ADDR[1]),
|
||||
.ADA2(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[2] : PORT_W_ADDR[2]),
|
||||
.ADA3(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[3] : PORT_W_ADDR[3]),
|
||||
.ADA4(PORT_W_ADDR[4]),
|
||||
.ADA5(PORT_W_ADDR[5]),
|
||||
.ADA6(PORT_W_ADDR[6]),
|
||||
.ADA7(PORT_W_ADDR[7]),
|
||||
.ADA8(PORT_W_ADDR[8]),
|
||||
.ADA9(PORT_W_ADDR[9]),
|
||||
.ADA10(PORT_W_ADDR[10]),
|
||||
.ADA11(PORT_W_ADDR[11]),
|
||||
.ADA12(PORT_W_ADDR[12]),
|
||||
.ADA13(PORT_W_ADDR[13]),
|
||||
.DIA0(DI[0]),
|
||||
.DIA1(DI[1]),
|
||||
.DIA2(DI[2]),
|
||||
.DIA3(DI[3]),
|
||||
.DIA4(DI[4]),
|
||||
.DIA5(DI[5]),
|
||||
.DIA6(DI[6]),
|
||||
.DIA7(DI[7]),
|
||||
.DIA8(DI[8]),
|
||||
.DIA9(DI[9]),
|
||||
.DIA10(DI[10]),
|
||||
.DIA11(DI[11]),
|
||||
.DIA12(DI[12]),
|
||||
.DIA13(DI[13]),
|
||||
.DIA14(DI[14]),
|
||||
.DIA15(DI[15]),
|
||||
.DIA16(DI[16]),
|
||||
.DIA17(DI[17]),
|
||||
.DIB0(DI[18]),
|
||||
.DIB1(DI[19]),
|
||||
.DIB2(DI[20]),
|
||||
.DIB3(DI[21]),
|
||||
.DIB4(DI[22]),
|
||||
.DIB5(DI[23]),
|
||||
.DIB6(DI[24]),
|
||||
.DIB7(DI[25]),
|
||||
.DIB8(DI[26]),
|
||||
.DIB9(DI[27]),
|
||||
.DIB10(DI[28]),
|
||||
.DIB11(DI[29]),
|
||||
.DIB12(DI[30]),
|
||||
.DIB13(DI[31]),
|
||||
.DIB14(DI[32]),
|
||||
.DIB15(DI[33]),
|
||||
.DIB16(DI[34]),
|
||||
.DIB17(DI[35]),
|
||||
|
||||
.CLKB(PORT_R_CLK),
|
||||
.WEB(1'b0),
|
||||
.CEB(PORT_R_CLK_EN),
|
||||
.OCEB(1'b1),
|
||||
.RSTB(OPTION_RESETMODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST),
|
||||
.CSB0(1'b0),
|
||||
.CSB1(1'b0),
|
||||
.CSB2(1'b0),
|
||||
.ADB0(PORT_R_ADDR[0]),
|
||||
.ADB1(PORT_R_ADDR[1]),
|
||||
.ADB2(PORT_R_ADDR[2]),
|
||||
.ADB3(PORT_R_ADDR[3]),
|
||||
.ADB4(PORT_R_ADDR[4]),
|
||||
.ADB5(PORT_R_ADDR[5]),
|
||||
.ADB6(PORT_R_ADDR[6]),
|
||||
.ADB7(PORT_R_ADDR[7]),
|
||||
.ADB8(PORT_R_ADDR[8]),
|
||||
.ADB9(PORT_R_ADDR[9]),
|
||||
.ADB10(PORT_R_ADDR[10]),
|
||||
.ADB11(PORT_R_ADDR[11]),
|
||||
.ADB12(PORT_R_ADDR[12]),
|
||||
.ADB13(PORT_R_ADDR[13]),
|
||||
.DOA0(DO[0]),
|
||||
.DOA1(DO[1]),
|
||||
.DOA2(DO[2]),
|
||||
.DOA3(DO[3]),
|
||||
.DOA4(DO[4]),
|
||||
.DOA5(DO[5]),
|
||||
.DOA6(DO[6]),
|
||||
.DOA7(DO[7]),
|
||||
.DOA8(DO[8]),
|
||||
.DOA9(DO[9]),
|
||||
.DOA10(DO[10]),
|
||||
.DOA11(DO[11]),
|
||||
.DOA12(DO[12]),
|
||||
.DOA13(DO[13]),
|
||||
.DOA14(DO[14]),
|
||||
.DOA15(DO[15]),
|
||||
.DOA16(DO[16]),
|
||||
.DOA17(DO[17]),
|
||||
.DOB0(DO[18]),
|
||||
.DOB1(DO[19]),
|
||||
.DOB2(DO[20]),
|
||||
.DOB3(DO[21]),
|
||||
.DOB4(DO[22]),
|
||||
.DOB5(DO[23]),
|
||||
.DOB6(DO[24]),
|
||||
.DOB7(DO[25]),
|
||||
.DOB8(DO[26]),
|
||||
.DOB9(DO[27]),
|
||||
.DOB10(DO[28]),
|
||||
.DOB11(DO[29]),
|
||||
.DOB12(DO[30]),
|
||||
.DOB13(DO[31]),
|
||||
.DOB14(DO[32]),
|
||||
.DOB15(DO[33]),
|
||||
.DOB16(DO[34]),
|
||||
.DOB17(DO[35]),
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,850 +0,0 @@
|
|||
// ECP5 Blackbox cells
|
||||
// FIXME: Create sim models
|
||||
|
||||
(* blackbox *)
|
||||
module MULT18X18D(
|
||||
input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17,
|
||||
input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17,
|
||||
input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17,
|
||||
input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB,
|
||||
input CLK0, CLK1, CLK2, CLK3,
|
||||
input CE0, CE1, CE2, CE3,
|
||||
input RST0, RST1, RST2, RST3,
|
||||
input SRIA0, SRIA1, SRIA2, SRIA3, SRIA4, SRIA5, SRIA6, SRIA7, SRIA8, SRIA9, SRIA10, SRIA11, SRIA12, SRIA13, SRIA14, SRIA15, SRIA16, SRIA17,
|
||||
input SRIB0, SRIB1, SRIB2, SRIB3, SRIB4, SRIB5, SRIB6, SRIB7, SRIB8, SRIB9, SRIB10, SRIB11, SRIB12, SRIB13, SRIB14, SRIB15, SRIB16, SRIB17,
|
||||
output SROA0, SROA1, SROA2, SROA3, SROA4, SROA5, SROA6, SROA7, SROA8, SROA9, SROA10, SROA11, SROA12, SROA13, SROA14, SROA15, SROA16, SROA17,
|
||||
output SROB0, SROB1, SROB2, SROB3, SROB4, SROB5, SROB6, SROB7, SROB8, SROB9, SROB10, SROB11, SROB12, SROB13, SROB14, SROB15, SROB16, SROB17,
|
||||
output ROA0, ROA1, ROA2, ROA3, ROA4, ROA5, ROA6, ROA7, ROA8, ROA9, ROA10, ROA11, ROA12, ROA13, ROA14, ROA15, ROA16, ROA17,
|
||||
output ROB0, ROB1, ROB2, ROB3, ROB4, ROB5, ROB6, ROB7, ROB8, ROB9, ROB10, ROB11, ROB12, ROB13, ROB14, ROB15, ROB16, ROB17,
|
||||
output ROC0, ROC1, ROC2, ROC3, ROC4, ROC5, ROC6, ROC7, ROC8, ROC9, ROC10, ROC11, ROC12, ROC13, ROC14, ROC15, ROC16, ROC17,
|
||||
output P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35,
|
||||
output SIGNEDP
|
||||
);
|
||||
parameter REG_INPUTA_CLK = "NONE";
|
||||
parameter REG_INPUTA_CE = "CE0";
|
||||
parameter REG_INPUTA_RST = "RST0";
|
||||
parameter REG_INPUTB_CLK = "NONE";
|
||||
parameter REG_INPUTB_CE = "CE0";
|
||||
parameter REG_INPUTB_RST = "RST0";
|
||||
parameter REG_INPUTC_CLK = "NONE";
|
||||
parameter REG_INPUTC_CE = "CE0";
|
||||
parameter REG_INPUTC_RST = "RST0";
|
||||
parameter REG_PIPELINE_CLK = "NONE";
|
||||
parameter REG_PIPELINE_CE = "CE0";
|
||||
parameter REG_PIPELINE_RST = "RST0";
|
||||
parameter REG_OUTPUT_CLK = "NONE";
|
||||
parameter REG_OUTPUT_CE = "CE0";
|
||||
parameter REG_OUTPUT_RST = "RST0";
|
||||
parameter [127:0] CLK0_DIV = "ENABLED";
|
||||
parameter [127:0] CLK1_DIV = "ENABLED";
|
||||
parameter [127:0] CLK2_DIV = "ENABLED";
|
||||
parameter [127:0] CLK3_DIV = "ENABLED";
|
||||
parameter HIGHSPEED_CLK = "NONE";
|
||||
parameter [127:0] GSR = "ENABLED";
|
||||
parameter CAS_MATCH_REG = "FALSE";
|
||||
parameter [127:0] SOURCEB_MODE = "B_SHIFT";
|
||||
parameter [127:0] MULT_BYPASS = "DISABLED";
|
||||
parameter [127:0] RESETMODE = "SYNC";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module ALU54B(
|
||||
input CLK0, CLK1, CLK2, CLK3,
|
||||
input CE0, CE1, CE2, CE3,
|
||||
input RST0, RST1, RST2, RST3,
|
||||
input SIGNEDIA, SIGNEDIB, SIGNEDCIN,
|
||||
input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, A32, A33, A34, A35,
|
||||
input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, B19, B20, B21, B22, B23, B24, B25, B26, B27, B28, B29, B30, B31, B32, B33, B34, B35,
|
||||
input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53,
|
||||
input CFB0, CFB1, CFB2, CFB3, CFB4, CFB5, CFB6, CFB7, CFB8, CFB9, CFB10, CFB11, CFB12, CFB13, CFB14, CFB15, CFB16, CFB17, CFB18, CFB19, CFB20, CFB21, CFB22, CFB23, CFB24, CFB25, CFB26, CFB27, CFB28, CFB29, CFB30, CFB31, CFB32, CFB33, CFB34, CFB35, CFB36, CFB37, CFB38, CFB39, CFB40, CFB41, CFB42, CFB43, CFB44, CFB45, CFB46, CFB47, CFB48, CFB49, CFB50, CFB51, CFB52, CFB53,
|
||||
input MA0, MA1, MA2, MA3, MA4, MA5, MA6, MA7, MA8, MA9, MA10, MA11, MA12, MA13, MA14, MA15, MA16, MA17, MA18, MA19, MA20, MA21, MA22, MA23, MA24, MA25, MA26, MA27, MA28, MA29, MA30, MA31, MA32, MA33, MA34, MA35,
|
||||
input MB0, MB1, MB2, MB3, MB4, MB5, MB6, MB7, MB8, MB9, MB10, MB11, MB12, MB13, MB14, MB15, MB16, MB17, MB18, MB19, MB20, MB21, MB22, MB23, MB24, MB25, MB26, MB27, MB28, MB29, MB30, MB31, MB32, MB33, MB34, MB35,
|
||||
input CIN0, CIN1, CIN2, CIN3, CIN4, CIN5, CIN6, CIN7, CIN8, CIN9, CIN10, CIN11, CIN12, CIN13, CIN14, CIN15, CIN16, CIN17, CIN18, CIN19, CIN20, CIN21, CIN22, CIN23, CIN24, CIN25, CIN26, CIN27, CIN28, CIN29, CIN30, CIN31, CIN32, CIN33, CIN34, CIN35, CIN36, CIN37, CIN38, CIN39, CIN40, CIN41, CIN42, CIN43, CIN44, CIN45, CIN46, CIN47, CIN48, CIN49, CIN50, CIN51, CIN52, CIN53,
|
||||
input OP0, OP1, OP2, OP3, OP4, OP5, OP6, OP7, OP8, OP9, OP10,
|
||||
output R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53,
|
||||
output CO0, CO1, CO2, CO3, CO4, CO5, CO6, CO7, CO8, CO9, CO10, CO11, CO12, CO13, CO14, CO15, CO16, CO17, CO18, CO19, CO20, CO21, CO22, CO23, CO24, CO25, CO26, CO27, CO28, CO29, CO30, CO31, CO32, CO33, CO34, CO35, CO36, CO37, CO38, CO39, CO40, CO41, CO42, CO43, CO44, CO45, CO46, CO47, CO48, CO49, CO50, CO51, CO52, CO53,
|
||||
output EQZ, EQZM, EQOM, EQPAT, EQPATB,
|
||||
output OVER, UNDER, OVERUNDER,
|
||||
output SIGNEDR
|
||||
);
|
||||
parameter REG_INPUTC0_CLK = "NONE";
|
||||
parameter REG_INPUTC0_CE = "CE0";
|
||||
parameter REG_INPUTC0_RST = "RST0";
|
||||
parameter REG_INPUTC1_CLK = "NONE";
|
||||
parameter REG_INPUTC1_CE = "CE0";
|
||||
parameter REG_INPUTC1_RST = "RST0";
|
||||
parameter REG_OPCODEOP0_0_CLK = "NONE";
|
||||
parameter REG_OPCODEOP0_0_CE = "CE0";
|
||||
parameter REG_OPCODEOP0_0_RST = "RST0";
|
||||
parameter REG_OPCODEOP1_0_CLK = "NONE";
|
||||
parameter REG_OPCODEOP0_1_CLK = "NONE";
|
||||
parameter REG_OPCODEOP0_1_CE = "CE0";
|
||||
parameter REG_OPCODEOP0_1_RST = "RST0";
|
||||
parameter REG_OPCODEOP1_1_CLK = "NONE";
|
||||
parameter REG_OPCODEIN_0_CLK = "NONE";
|
||||
parameter REG_OPCODEIN_0_CE = "CE0";
|
||||
parameter REG_OPCODEIN_0_RST = "RST0";
|
||||
parameter REG_OPCODEIN_1_CLK = "NONE";
|
||||
parameter REG_OPCODEIN_1_CE = "CE0";
|
||||
parameter REG_OPCODEIN_1_RST = "RST0";
|
||||
parameter REG_OUTPUT0_CLK = "NONE";
|
||||
parameter REG_OUTPUT0_CE = "CE0";
|
||||
parameter REG_OUTPUT0_RST = "RST0";
|
||||
parameter REG_OUTPUT1_CLK = "NONE";
|
||||
parameter REG_OUTPUT1_CE = "CE0";
|
||||
parameter REG_OUTPUT1_RST = "RST0";
|
||||
parameter REG_FLAG_CLK = "NONE";
|
||||
parameter REG_FLAG_CE = "CE0";
|
||||
parameter REG_FLAG_RST = "RST0";
|
||||
parameter REG_INPUTCFB_CLK = "NONE";
|
||||
parameter REG_INPUTCFB_CE = "CE0";
|
||||
parameter REG_INPUTCFB_RST = "RST0";
|
||||
parameter [127:0] MCPAT_SOURCE = "STATIC";
|
||||
parameter [127:0] MASKPAT_SOURCE = "STATIC";
|
||||
parameter MASK01 = "0x00000000000000";
|
||||
parameter [127:0] CLK0_DIV = "ENABLED";
|
||||
parameter [127:0] CLK1_DIV = "ENABLED";
|
||||
parameter [127:0] CLK2_DIV = "ENABLED";
|
||||
parameter [127:0] CLK3_DIV = "ENABLED";
|
||||
parameter MCPAT = "0x00000000000000";
|
||||
parameter MASKPAT = "0x00000000000000";
|
||||
parameter RNDPAT = "0x00000000000000";
|
||||
parameter [127:0] GSR = "ENABLED";
|
||||
parameter [127:0] RESETMODE = "SYNC";
|
||||
parameter MULT9_MODE = "DISABLED";
|
||||
parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED";
|
||||
parameter LEGACY = "DISABLED";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module EHXPLLL (
|
||||
input CLKI, CLKFB,
|
||||
input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG,
|
||||
input STDBY, PLLWAKESYNC,
|
||||
input RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3,
|
||||
output CLKOP, CLKOS, CLKOS2, CLKOS3,
|
||||
output LOCK, INTLOCK,
|
||||
output REFCLK, CLKINTFB
|
||||
);
|
||||
parameter CLKI_DIV = 1;
|
||||
parameter CLKFB_DIV = 1;
|
||||
parameter CLKOP_DIV = 8;
|
||||
parameter CLKOS_DIV = 8;
|
||||
parameter CLKOS2_DIV = 8;
|
||||
parameter CLKOS3_DIV = 8;
|
||||
parameter CLKOP_ENABLE = "ENABLED";
|
||||
parameter CLKOS_ENABLE = "DISABLED";
|
||||
parameter CLKOS2_ENABLE = "DISABLED";
|
||||
parameter CLKOS3_ENABLE = "DISABLED";
|
||||
parameter CLKOP_CPHASE = 0;
|
||||
parameter CLKOS_CPHASE = 0;
|
||||
parameter CLKOS2_CPHASE = 0;
|
||||
parameter CLKOS3_CPHASE = 0;
|
||||
parameter CLKOP_FPHASE = 0;
|
||||
parameter CLKOS_FPHASE = 0;
|
||||
parameter CLKOS2_FPHASE = 0;
|
||||
parameter CLKOS3_FPHASE = 0;
|
||||
parameter FEEDBK_PATH = "CLKOP";
|
||||
parameter CLKOP_TRIM_POL = "RISING";
|
||||
parameter CLKOP_TRIM_DELAY = 0;
|
||||
parameter CLKOS_TRIM_POL = "RISING";
|
||||
parameter CLKOS_TRIM_DELAY = 0;
|
||||
parameter OUTDIVIDER_MUXA = "DIVA";
|
||||
parameter OUTDIVIDER_MUXB = "DIVB";
|
||||
parameter OUTDIVIDER_MUXC = "DIVC";
|
||||
parameter OUTDIVIDER_MUXD = "DIVD";
|
||||
parameter PLL_LOCK_MODE = 0;
|
||||
parameter PLL_LOCK_DELAY = 200;
|
||||
parameter STDBY_ENABLE = "DISABLED";
|
||||
parameter REFIN_RESET = "DISABLED";
|
||||
parameter SYNC_ENABLE = "DISABLED";
|
||||
parameter INT_LOCK_STICKY = "ENABLED";
|
||||
parameter DPHASE_SOURCE = "DISABLED";
|
||||
parameter PLLRST_ENA = "DISABLED";
|
||||
parameter INTFB_WAKE = "DISABLED";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DTR(
|
||||
input STARTPULSE,
|
||||
output DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0
|
||||
);
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module OSCG(
|
||||
output OSC
|
||||
);
|
||||
parameter DIV = 128;
|
||||
endmodule
|
||||
|
||||
(* blackbox *) (* keep *)
|
||||
module USRMCLK(
|
||||
input USRMCLKI, USRMCLKTS,
|
||||
output USRMCLKO
|
||||
);
|
||||
endmodule
|
||||
|
||||
(* blackbox *) (* keep *)
|
||||
module JTAGG(
|
||||
(* iopad_external_pin *)
|
||||
input TCK,
|
||||
(* iopad_external_pin *)
|
||||
input TMS,
|
||||
(* iopad_external_pin *)
|
||||
input TDI,
|
||||
input JTDO2, JTDO1,
|
||||
(* iopad_external_pin *)
|
||||
output TDO,
|
||||
output JTDI, JTCK, JRTI2, JRTI1,
|
||||
output JSHIFT, JUPDATE, JRSTN, JCE2, JCE1
|
||||
);
|
||||
parameter ER1 = "ENABLED";
|
||||
parameter ER2 = "ENABLED";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DELAYF(
|
||||
input A, LOADN, MOVE, DIRECTION,
|
||||
output Z, CFLAG
|
||||
);
|
||||
parameter DEL_MODE = "USER_DEFINED";
|
||||
parameter DEL_VALUE = 0;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DELAYG(
|
||||
input A,
|
||||
output Z
|
||||
);
|
||||
parameter DEL_MODE = "USER_DEFINED";
|
||||
parameter DEL_VALUE = 0;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module IDDRX1F(
|
||||
input D, SCLK, RST,
|
||||
output Q0, Q1
|
||||
);
|
||||
parameter GSR = "ENABLED";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module IDDRX2F(
|
||||
input D, SCLK, ECLK, RST, ALIGNWD,
|
||||
output Q0, Q1, Q2, Q3
|
||||
);
|
||||
parameter GSR = "ENABLED";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module IDDR71B(
|
||||
input D, SCLK, ECLK, RST, ALIGNWD,
|
||||
output Q0, Q1, Q2, Q3, Q4, Q5, Q6
|
||||
);
|
||||
parameter GSR = "ENABLED";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module IDDRX2DQA(
|
||||
input D, DQSR90, ECLK, SCLK, RST,
|
||||
input RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0,
|
||||
output Q0, Q1, Q2, Q3, QWL
|
||||
);
|
||||
parameter GSR = "ENABLED";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module ODDRX1F(
|
||||
input SCLK, RST, D0, D1,
|
||||
output Q
|
||||
);
|
||||
parameter GSR = "ENABLED";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module ODDRX2F(
|
||||
input SCLK, ECLK, RST, D0, D1, D2, D3,
|
||||
output Q
|
||||
);
|
||||
parameter GSR = "ENABLED";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module ODDR71B(
|
||||
input SCLK, ECLK, RST, D0, D1, D2, D3, D4, D5, D6,
|
||||
output Q
|
||||
);
|
||||
parameter GSR = "ENABLED";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module OSHX2A(
|
||||
input D0, D1, RST, ECLK, SCLK,
|
||||
output Q
|
||||
);
|
||||
parameter GSR = "ENABLED";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module ODDRX2DQA(
|
||||
input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW270,
|
||||
output Q
|
||||
);
|
||||
parameter GSR = "ENABLED";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module ODDRX2DQSB(
|
||||
input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW,
|
||||
output Q
|
||||
);
|
||||
parameter GSR = "ENABLED";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module TSHX2DQA(
|
||||
input T0, T1, SCLK, ECLK, DQSW270, RST,
|
||||
output Q
|
||||
);
|
||||
parameter GSR = "ENABLED";
|
||||
parameter REGSET = "SET";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module TSHX2DQSA(
|
||||
input T0, T1, SCLK, ECLK, DQSW, RST,
|
||||
output Q
|
||||
);
|
||||
parameter GSR = "ENABLED";
|
||||
parameter REGSET = "SET";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DQSBUFM(
|
||||
input DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL,
|
||||
input ECLK, SCLK,
|
||||
input DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4,
|
||||
input DYNDELAY3, DYNDELAY2, DYNDELAY1, DYNDELAY0,
|
||||
input RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE,
|
||||
output DQSR90, DQSW, DQSW270,
|
||||
output RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0,
|
||||
output DATAVALID, BURSTDET, RDCFLAG, WRCFLAG
|
||||
);
|
||||
parameter DQS_LI_DEL_ADJ = "FACTORYONLY";
|
||||
parameter DQS_LI_DEL_VAL = 0;
|
||||
parameter DQS_LO_DEL_ADJ = "FACTORYONLY";
|
||||
parameter DQS_LO_DEL_VAL = 0;
|
||||
parameter GSR = "ENABLED";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DDRDLLA(
|
||||
input CLK, RST, UDDCNTLN, FREEZE,
|
||||
output LOCK, DDRDEL, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0
|
||||
);
|
||||
parameter FORCE_MAX_DELAY = "NO";
|
||||
parameter GSR = "ENABLED";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DLLDELD(
|
||||
input A, DDRDEL, LOADN, MOVE, DIRECTION,
|
||||
output Z, CFLAG
|
||||
);
|
||||
parameter DEL_ADJ = "PLUS";
|
||||
parameter DEL_VAL = 0;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module CLKDIVF(
|
||||
input CLKI, RST, ALIGNWD,
|
||||
output CDIVX
|
||||
);
|
||||
parameter GSR = "DISABLED";
|
||||
parameter DIV = "2.0";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module ECLKSYNCB(
|
||||
input ECLKI, STOP,
|
||||
output ECLKO
|
||||
);
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module ECLKBRIDGECS(
|
||||
input CLK0, CLK1, SEL,
|
||||
output ECSOUT
|
||||
);
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DCCA(
|
||||
input CLKI, CE,
|
||||
output CLKO
|
||||
);
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DCSC(
|
||||
input CLK1, CLK0,
|
||||
input SEL1, SEL0,
|
||||
input MODESEL,
|
||||
output DCSOUT
|
||||
);
|
||||
parameter DCSMODE = "POS";
|
||||
endmodule
|
||||
|
||||
(* blackbox *) (* keep *)
|
||||
module DCUA(
|
||||
(* iopad_external_pin *)
|
||||
input CH0_HDINP,
|
||||
(* iopad_external_pin *)
|
||||
input CH1_HDINP,
|
||||
(* iopad_external_pin *)
|
||||
input CH0_HDINN,
|
||||
(* iopad_external_pin *)
|
||||
input CH1_HDINN,
|
||||
input D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND,
|
||||
input CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK,
|
||||
input CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3,
|
||||
input CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7,
|
||||
input CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11,
|
||||
input CH0_FF_TX_D_12, CH1_FF_TX_D_12, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15,
|
||||
input CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19,
|
||||
input CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23, CH1_FF_TX_D_23,
|
||||
input CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX,
|
||||
input CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP,
|
||||
input CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE,
|
||||
input CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST,
|
||||
input CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX,
|
||||
input D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7,
|
||||
input D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX,
|
||||
input CH0_SCIEN, CH1_SCIEN, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE,
|
||||
input D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0,
|
||||
input D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7, D_SCAN_MODE,
|
||||
input D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6,D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11,
|
||||
output CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND, D_TXPLL_LOL_TO_ND,
|
||||
output CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK,
|
||||
output CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1,
|
||||
output CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5,
|
||||
output CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9,
|
||||
output CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13,
|
||||
output CH0_FF_RX_D_14, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17,
|
||||
output CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21,
|
||||
output CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON,
|
||||
output CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN,
|
||||
output CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED,
|
||||
output CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3,
|
||||
output D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7,
|
||||
output D_COUT0, D_COUT1, D_COUT2, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19,
|
||||
|
||||
input D_REFCLKI,
|
||||
output D_FFS_PLOL
|
||||
);
|
||||
parameter CH0_AUTO_CALIB_EN = "0b0";
|
||||
parameter CH0_AUTO_FACQ_EN = "0b0";
|
||||
parameter CH0_BAND_THRESHOLD = "0b000000";
|
||||
parameter CH0_CALIB_CK_MODE = "0b0";
|
||||
parameter CH0_CC_MATCH_1 = "0b0000000000";
|
||||
parameter CH0_CC_MATCH_2 = "0b0000000000";
|
||||
parameter CH0_CC_MATCH_3 = "0b0000000000";
|
||||
parameter CH0_CC_MATCH_4 = "0b0000000000";
|
||||
parameter CH0_CDR_CNT4SEL = "0b00";
|
||||
parameter CH0_CDR_CNT8SEL = "0b00";
|
||||
parameter CH0_CTC_BYPASS = "0b0";
|
||||
parameter CH0_DCOATDCFG = "0b00";
|
||||
parameter CH0_DCOATDDLY = "0b00";
|
||||
parameter CH0_DCOBYPSATD = "0b0";
|
||||
parameter CH0_DCOCALDIV = "0b000";
|
||||
parameter CH0_DCOCTLGI = "0b000";
|
||||
parameter CH0_DCODISBDAVOID = "0b0";
|
||||
parameter CH0_DCOFLTDAC = "0b00";
|
||||
parameter CH0_DCOFTNRG = "0b000";
|
||||
parameter CH0_DCOIOSTUNE = "0b000";
|
||||
parameter CH0_DCOITUNE = "0b00";
|
||||
parameter CH0_DCOITUNE4LSB = "0b000";
|
||||
parameter CH0_DCOIUPDNX2 = "0b0";
|
||||
parameter CH0_DCONUOFLSB = "0b000";
|
||||
parameter CH0_DCOSCALEI = "0b00";
|
||||
parameter CH0_DCOSTARTVAL = "0b000";
|
||||
parameter CH0_DCOSTEP = "0b00";
|
||||
parameter CH0_DEC_BYPASS = "0b0";
|
||||
parameter CH0_ENABLE_CG_ALIGN = "0b0";
|
||||
parameter CH0_ENC_BYPASS = "0b0";
|
||||
parameter CH0_FF_RX_F_CLK_DIS = "0b0";
|
||||
parameter CH0_FF_RX_H_CLK_EN = "0b0";
|
||||
parameter CH0_FF_TX_F_CLK_DIS = "0b0";
|
||||
parameter CH0_FF_TX_H_CLK_EN = "0b0";
|
||||
parameter CH0_GE_AN_ENABLE = "0b0";
|
||||
parameter CH0_INVERT_RX = "0b0";
|
||||
parameter CH0_INVERT_TX = "0b0";
|
||||
parameter CH0_LDR_CORE2TX_SEL = "0b0";
|
||||
parameter CH0_LDR_RX2CORE_SEL = "0b0";
|
||||
parameter CH0_LEQ_OFFSET_SEL = "0b0";
|
||||
parameter CH0_LEQ_OFFSET_TRIM = "0b000";
|
||||
parameter CH0_LSM_DISABLE = "0b0";
|
||||
parameter CH0_MATCH_2_ENABLE = "0b0";
|
||||
parameter CH0_MATCH_4_ENABLE = "0b0";
|
||||
parameter CH0_MIN_IPG_CNT = "0b00";
|
||||
parameter CH0_PCIE_EI_EN = "0b0";
|
||||
parameter CH0_PCIE_MODE = "0b0";
|
||||
parameter CH0_PCS_DET_TIME_SEL = "0b00";
|
||||
parameter CH0_PDEN_SEL = "0b0";
|
||||
parameter CH0_PRBS_ENABLE = "0b0";
|
||||
parameter CH0_PRBS_LOCK = "0b0";
|
||||
parameter CH0_PRBS_SELECTION = "0b0";
|
||||
parameter CH0_RATE_MODE_RX = "0b0";
|
||||
parameter CH0_RATE_MODE_TX = "0b0";
|
||||
parameter CH0_RCV_DCC_EN = "0b0";
|
||||
parameter CH0_REG_BAND_OFFSET = "0b0000";
|
||||
parameter CH0_REG_BAND_SEL = "0b000000";
|
||||
parameter CH0_REG_IDAC_EN = "0b0";
|
||||
parameter CH0_REG_IDAC_SEL = "0b0000000000";
|
||||
parameter CH0_REQ_EN = "0b0";
|
||||
parameter CH0_REQ_LVL_SET = "0b00";
|
||||
parameter CH0_RIO_MODE = "0b0";
|
||||
parameter CH0_RLOS_SEL = "0b0";
|
||||
parameter CH0_RPWDNB = "0b0";
|
||||
parameter CH0_RTERM_RX = "0b00000";
|
||||
parameter CH0_RTERM_TX = "0b00000";
|
||||
parameter CH0_RXIN_CM = "0b00";
|
||||
parameter CH0_RXTERM_CM = "0b00";
|
||||
parameter CH0_RX_DCO_CK_DIV = "0b000";
|
||||
parameter CH0_RX_DIV11_SEL = "0b0";
|
||||
parameter CH0_RX_GEAR_BYPASS = "0b0";
|
||||
parameter CH0_RX_GEAR_MODE = "0b0";
|
||||
parameter CH0_RX_LOS_CEQ = "0b00";
|
||||
parameter CH0_RX_LOS_EN = "0b0";
|
||||
parameter CH0_RX_LOS_HYST_EN = "0b0";
|
||||
parameter CH0_RX_LOS_LVL = "0b000";
|
||||
parameter CH0_RX_RATE_SEL = "0b0000";
|
||||
parameter CH0_RX_SB_BYPASS = "0b0";
|
||||
parameter CH0_SB_BYPASS = "0b0";
|
||||
parameter CH0_SEL_SD_RX_CLK = "0b0";
|
||||
parameter CH0_TDRV_DAT_SEL = "0b00";
|
||||
parameter CH0_TDRV_POST_EN = "0b0";
|
||||
parameter CH0_TDRV_PRE_EN = "0b0";
|
||||
parameter CH0_TDRV_SLICE0_CUR = "0b000";
|
||||
parameter CH0_TDRV_SLICE0_SEL = "0b00";
|
||||
parameter CH0_TDRV_SLICE1_CUR = "0b000";
|
||||
parameter CH0_TDRV_SLICE1_SEL = "0b00";
|
||||
parameter CH0_TDRV_SLICE2_CUR = "0b00";
|
||||
parameter CH0_TDRV_SLICE2_SEL = "0b00";
|
||||
parameter CH0_TDRV_SLICE3_CUR = "0b00";
|
||||
parameter CH0_TDRV_SLICE3_SEL = "0b00";
|
||||
parameter CH0_TDRV_SLICE4_CUR = "0b00";
|
||||
parameter CH0_TDRV_SLICE4_SEL = "0b00";
|
||||
parameter CH0_TDRV_SLICE5_CUR = "0b00";
|
||||
parameter CH0_TDRV_SLICE5_SEL = "0b00";
|
||||
parameter CH0_TPWDNB = "0b0";
|
||||
parameter CH0_TX_CM_SEL = "0b00";
|
||||
parameter CH0_TX_DIV11_SEL = "0b0";
|
||||
parameter CH0_TX_GEAR_BYPASS = "0b0";
|
||||
parameter CH0_TX_GEAR_MODE = "0b0";
|
||||
parameter CH0_TX_POST_SIGN = "0b0";
|
||||
parameter CH0_TX_PRE_SIGN = "0b0";
|
||||
parameter CH0_UC_MODE = "0b0";
|
||||
parameter CH0_UDF_COMMA_A = "0b0000000000";
|
||||
parameter CH0_UDF_COMMA_B = "0b0000000000";
|
||||
parameter CH0_UDF_COMMA_MASK = "0b0000000000";
|
||||
parameter CH0_WA_BYPASS = "0b0";
|
||||
parameter CH0_WA_MODE = "0b0";
|
||||
parameter CH1_AUTO_CALIB_EN = "0b0";
|
||||
parameter CH1_AUTO_FACQ_EN = "0b0";
|
||||
parameter CH1_BAND_THRESHOLD = "0b000000";
|
||||
parameter CH1_CALIB_CK_MODE = "0b0";
|
||||
parameter CH1_CC_MATCH_1 = "0b0000000000";
|
||||
parameter CH1_CC_MATCH_2 = "0b0000000000";
|
||||
parameter CH1_CC_MATCH_3 = "0b0000000000";
|
||||
parameter CH1_CC_MATCH_4 = "0b0000000000";
|
||||
parameter CH1_CDR_CNT4SEL = "0b00";
|
||||
parameter CH1_CDR_CNT8SEL = "0b00";
|
||||
parameter CH1_CTC_BYPASS = "0b0";
|
||||
parameter CH1_DCOATDCFG = "0b00";
|
||||
parameter CH1_DCOATDDLY = "0b00";
|
||||
parameter CH1_DCOBYPSATD = "0b0";
|
||||
parameter CH1_DCOCALDIV = "0b000";
|
||||
parameter CH1_DCOCTLGI = "0b000";
|
||||
parameter CH1_DCODISBDAVOID = "0b0";
|
||||
parameter CH1_DCOFLTDAC = "0b00";
|
||||
parameter CH1_DCOFTNRG = "0b000";
|
||||
parameter CH1_DCOIOSTUNE = "0b000";
|
||||
parameter CH1_DCOITUNE = "0b00";
|
||||
parameter CH1_DCOITUNE4LSB = "0b000";
|
||||
parameter CH1_DCOIUPDNX2 = "0b0";
|
||||
parameter CH1_DCONUOFLSB = "0b000";
|
||||
parameter CH1_DCOSCALEI = "0b00";
|
||||
parameter CH1_DCOSTARTVAL = "0b000";
|
||||
parameter CH1_DCOSTEP = "0b00";
|
||||
parameter CH1_DEC_BYPASS = "0b0";
|
||||
parameter CH1_ENABLE_CG_ALIGN = "0b0";
|
||||
parameter CH1_ENC_BYPASS = "0b0";
|
||||
parameter CH1_FF_RX_F_CLK_DIS = "0b0";
|
||||
parameter CH1_FF_RX_H_CLK_EN = "0b0";
|
||||
parameter CH1_FF_TX_F_CLK_DIS = "0b0";
|
||||
parameter CH1_FF_TX_H_CLK_EN = "0b0";
|
||||
parameter CH1_GE_AN_ENABLE = "0b0";
|
||||
parameter CH1_INVERT_RX = "0b0";
|
||||
parameter CH1_INVERT_TX = "0b0";
|
||||
parameter CH1_LDR_CORE2TX_SEL = "0b0";
|
||||
parameter CH1_LDR_RX2CORE_SEL = "0b0";
|
||||
parameter CH1_LEQ_OFFSET_SEL = "0b0";
|
||||
parameter CH1_LEQ_OFFSET_TRIM = "0b000";
|
||||
parameter CH1_LSM_DISABLE = "0b0";
|
||||
parameter CH1_MATCH_2_ENABLE = "0b0";
|
||||
parameter CH1_MATCH_4_ENABLE = "0b0";
|
||||
parameter CH1_MIN_IPG_CNT = "0b00";
|
||||
parameter CH1_PCIE_EI_EN = "0b0";
|
||||
parameter CH1_PCIE_MODE = "0b0";
|
||||
parameter CH1_PCS_DET_TIME_SEL = "0b00";
|
||||
parameter CH1_PDEN_SEL = "0b0";
|
||||
parameter CH1_PRBS_ENABLE = "0b0";
|
||||
parameter CH1_PRBS_LOCK = "0b0";
|
||||
parameter CH1_PRBS_SELECTION = "0b0";
|
||||
parameter CH1_RATE_MODE_RX = "0b0";
|
||||
parameter CH1_RATE_MODE_TX = "0b0";
|
||||
parameter CH1_RCV_DCC_EN = "0b0";
|
||||
parameter CH1_REG_BAND_OFFSET = "0b0000";
|
||||
parameter CH1_REG_BAND_SEL = "0b000000";
|
||||
parameter CH1_REG_IDAC_EN = "0b0";
|
||||
parameter CH1_REG_IDAC_SEL = "0b0000000000";
|
||||
parameter CH1_REQ_EN = "0b0";
|
||||
parameter CH1_REQ_LVL_SET = "0b00";
|
||||
parameter CH1_RIO_MODE = "0b0";
|
||||
parameter CH1_RLOS_SEL = "0b0";
|
||||
parameter CH1_RPWDNB = "0b0";
|
||||
parameter CH1_RTERM_RX = "0b00000";
|
||||
parameter CH1_RTERM_TX = "0b00000";
|
||||
parameter CH1_RXIN_CM = "0b00";
|
||||
parameter CH1_RXTERM_CM = "0b00";
|
||||
parameter CH1_RX_DCO_CK_DIV = "0b000";
|
||||
parameter CH1_RX_DIV11_SEL = "0b0";
|
||||
parameter CH1_RX_GEAR_BYPASS = "0b0";
|
||||
parameter CH1_RX_GEAR_MODE = "0b0";
|
||||
parameter CH1_RX_LOS_CEQ = "0b00";
|
||||
parameter CH1_RX_LOS_EN = "0b0";
|
||||
parameter CH1_RX_LOS_HYST_EN = "0b0";
|
||||
parameter CH1_RX_LOS_LVL = "0b000";
|
||||
parameter CH1_RX_RATE_SEL = "0b0000";
|
||||
parameter CH1_RX_SB_BYPASS = "0b0";
|
||||
parameter CH1_SB_BYPASS = "0b0";
|
||||
parameter CH1_SEL_SD_RX_CLK = "0b0";
|
||||
parameter CH1_TDRV_DAT_SEL = "0b00";
|
||||
parameter CH1_TDRV_POST_EN = "0b0";
|
||||
parameter CH1_TDRV_PRE_EN = "0b0";
|
||||
parameter CH1_TDRV_SLICE0_CUR = "0b000";
|
||||
parameter CH1_TDRV_SLICE0_SEL = "0b00";
|
||||
parameter CH1_TDRV_SLICE1_CUR = "0b000";
|
||||
parameter CH1_TDRV_SLICE1_SEL = "0b00";
|
||||
parameter CH1_TDRV_SLICE2_CUR = "0b00";
|
||||
parameter CH1_TDRV_SLICE2_SEL = "0b00";
|
||||
parameter CH1_TDRV_SLICE3_CUR = "0b00";
|
||||
parameter CH1_TDRV_SLICE3_SEL = "0b00";
|
||||
parameter CH1_TDRV_SLICE4_CUR = "0b00";
|
||||
parameter CH1_TDRV_SLICE4_SEL = "0b00";
|
||||
parameter CH1_TDRV_SLICE5_CUR = "0b00";
|
||||
parameter CH1_TDRV_SLICE5_SEL = "0b00";
|
||||
parameter CH1_TPWDNB = "0b0";
|
||||
parameter CH1_TX_CM_SEL = "0b00";
|
||||
parameter CH1_TX_DIV11_SEL = "0b0";
|
||||
parameter CH1_TX_GEAR_BYPASS = "0b0";
|
||||
parameter CH1_TX_GEAR_MODE = "0b0";
|
||||
parameter CH1_TX_POST_SIGN = "0b0";
|
||||
parameter CH1_TX_PRE_SIGN = "0b0";
|
||||
parameter CH1_UC_MODE = "0b0";
|
||||
parameter CH1_UDF_COMMA_A = "0b0000000000";
|
||||
parameter CH1_UDF_COMMA_B = "0b0000000000";
|
||||
parameter CH1_UDF_COMMA_MASK = "0b0000000000";
|
||||
parameter CH1_WA_BYPASS = "0b0";
|
||||
parameter CH1_WA_MODE = "0b0";
|
||||
parameter D_BITCLK_FROM_ND_EN = "0b0";
|
||||
parameter D_BITCLK_LOCAL_EN = "0b0";
|
||||
parameter D_BITCLK_ND_EN = "0b0";
|
||||
parameter D_BUS8BIT_SEL = "0b0";
|
||||
parameter D_CDR_LOL_SET = "0b00";
|
||||
parameter D_CMUSETBIASI = "0b00";
|
||||
parameter D_CMUSETI4CPP = "0b0000";
|
||||
parameter D_CMUSETI4CPZ = "0b0000";
|
||||
parameter D_CMUSETI4VCO = "0b00";
|
||||
parameter D_CMUSETICP4P = "0b00";
|
||||
parameter D_CMUSETICP4Z = "0b000";
|
||||
parameter D_CMUSETINITVCT = "0b00";
|
||||
parameter D_CMUSETISCL4VCO = "0b000";
|
||||
parameter D_CMUSETP1GM = "0b000";
|
||||
parameter D_CMUSETP2AGM = "0b000";
|
||||
parameter D_CMUSETZGM = "0b000";
|
||||
parameter D_DCO_CALIB_TIME_SEL = "0b00";
|
||||
parameter D_HIGH_MARK = "0b0000";
|
||||
parameter D_IB_PWDNB = "0b0";
|
||||
parameter D_ISETLOS = "0b00000000";
|
||||
parameter D_LOW_MARK = "0b0000";
|
||||
parameter D_MACROPDB = "0b0";
|
||||
parameter D_PD_ISET = "0b00";
|
||||
parameter D_PLL_LOL_SET = "0b00";
|
||||
parameter D_REFCK_MODE = "0b000";
|
||||
parameter D_REQ_ISET = "0b000";
|
||||
parameter D_RG_EN = "0b0";
|
||||
parameter D_RG_SET = "0b00";
|
||||
parameter D_SETICONST_AUX = "0b00";
|
||||
parameter D_SETICONST_CH = "0b00";
|
||||
parameter D_SETIRPOLY_AUX = "0b00";
|
||||
parameter D_SETIRPOLY_CH = "0b00";
|
||||
parameter D_SETPLLRC = "0b000000";
|
||||
parameter D_SYNC_LOCAL_EN = "0b0";
|
||||
parameter D_SYNC_ND_EN = "0b0";
|
||||
parameter D_TXPLL_PWDNB = "0b0";
|
||||
parameter D_TX_VCO_CK_DIV = "0b000";
|
||||
parameter D_XGE_MODE = "0b0";
|
||||
|
||||
// These parameters don't do anything but are
|
||||
// needed for compatibility with Diamond
|
||||
parameter D_TX_MAX_RATE = "2.5";
|
||||
parameter D_RX_MAX_RATE = "2.5";
|
||||
parameter CH0_TXAMPLITUDE = "0d1300";
|
||||
parameter CH1_TXAMPLITUDE = "0d1300";
|
||||
parameter CH0_PROTOCOL = "8B10B";
|
||||
parameter CH1_PROTOCOL = "8B10B";
|
||||
parameter CH0_CDR_MAX_RATE = "2.5";
|
||||
parameter CH1_CDR_MAX_RATE = "2.5";
|
||||
parameter CH0_TXDEPRE = "DISABLED";
|
||||
parameter CH1_TXDEPRE = "DISABLED";
|
||||
parameter CH0_TXDEPOST = "DISABLED";
|
||||
parameter CH1_TXDEPOST = "DISABLED";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module EXTREFB (
|
||||
(* iopad_external_pin *)
|
||||
input REFCLKP,
|
||||
(* iopad_external_pin *)
|
||||
input REFCLKN,
|
||||
output REFCLKO
|
||||
);
|
||||
parameter REFCK_PWDNB = "0b0";
|
||||
parameter REFCK_RTERM = "0b0";
|
||||
parameter REFCK_DCBIAS_EN = "0b0";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module PCSCLKDIV (
|
||||
input CLKI, RST, SEL2, SEL1, SEL0,
|
||||
output CDIV1, CDIVX
|
||||
);
|
||||
parameter GSR = "DISABLED";
|
||||
endmodule
|
||||
|
||||
// Note: this module is not marked keep as we want it swept away in synth (sim use only)
|
||||
(* blackbox *)
|
||||
module PUR (
|
||||
input PUR
|
||||
);
|
||||
parameter RST_PULSE = 1;
|
||||
endmodule
|
||||
|
||||
(* blackbox, keep *)
|
||||
module GSR (
|
||||
input GSR
|
||||
);
|
||||
endmodule
|
||||
|
||||
(* blackbox, keep *)
|
||||
module SGSR (
|
||||
input GSR, CLK
|
||||
);
|
||||
endmodule
|
||||
|
||||
|
||||
(* blackbox *)
|
||||
module PDPW16KD (
|
||||
input DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28, DI27, DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18,
|
||||
input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
|
||||
input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0,
|
||||
input BE3, BE2, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0,
|
||||
input ADR13, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0,
|
||||
input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST,
|
||||
output DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28, DO27, DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18,
|
||||
output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0
|
||||
);
|
||||
parameter DATA_WIDTH_W = 36;
|
||||
parameter DATA_WIDTH_R = 36;
|
||||
parameter GSR = "ENABLED";
|
||||
|
||||
parameter REGMODE = "NOREG";
|
||||
|
||||
parameter RESETMODE = "SYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
|
||||
parameter CSDECODE_W = "0b000";
|
||||
parameter CSDECODE_R = "0b000";
|
||||
|
||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_DATA = "STATIC";
|
||||
parameter CLKWMUX = "CLKW";
|
||||
parameter CLKRMUX = "CLKR";
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
// Diamond flip-flops
|
||||
module FD1P3AX(input D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module FD1P3AY(input D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module FD1P3BX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module FD1P3DX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module FD1P3IX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module FD1P3JX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module FD1S3AX(input D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .DI(D), .Q(Q)); endmodule
|
||||
module FD1S3AY(input D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .DI(D), .Q(Q)); endmodule
|
||||
module FD1S3BX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
|
||||
module FD1S3DX(input CD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
|
||||
module FD1S3IX(input CD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
|
||||
module FD1S3JX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
|
||||
|
||||
// TODO: Diamond latches
|
||||
// module FL1P3AY(); endmodule
|
||||
// module FL1P3AZ(); endmodule
|
||||
// module FL1P3BX(); endmodule
|
||||
// module FL1P3DX(); endmodule
|
||||
// module FL1P3IY(); endmodule
|
||||
// module FL1P3JY(); endmodule
|
||||
// module FL1S3AX(); endmodule
|
||||
// module FL1S3AY(); endmodule
|
||||
|
||||
// Diamond I/O registers
|
||||
module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
|
||||
module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
|
||||
// TODO: Diamond I/O latches
|
||||
// module IFS1S1B(input PD, D, SCLK, output Q); endmodule
|
||||
// module IFS1S1D(input CD, D, SCLK, output Q); endmodule
|
||||
// module IFS1S1I(input PD, D, SCLK, output Q); endmodule
|
||||
// module IFS1S1J(input CD, D, SCLK, output Q); endmodule
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
// Diamond I/O buffers
|
||||
module IB ((* iopad_external_pin *) input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
|
||||
module IBPU ((* iopad_external_pin *) input I, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
|
||||
module IBPD ((* iopad_external_pin *) input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
|
||||
module OB (input I, (* iopad_external_pin *) output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule
|
||||
module OBZ (input I, T, (* iopad_external_pin *) output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
|
||||
module OBZPU(input I, T, (* iopad_external_pin *) output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
|
||||
module OBZPD(input I, T, (* iopad_external_pin *) output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
|
||||
module OBCO (input I, output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule
|
||||
module BB (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
|
||||
module BBPU (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
|
||||
module BBPD (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
|
||||
module ILVDS(input A, AN, (* iopad_external_pin *) output Z ); TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule
|
||||
module OLVDS(input A, (* iopad_external_pin *) output Z, output ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule
|
||||
|
|
@ -1,191 +0,0 @@
|
|||
module \$_DFF_N_ (input D, C, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));
|
||||
else
|
||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));
|
||||
endgenerate
|
||||
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
|
||||
endmodule
|
||||
|
||||
module \$_DFF_P_ (input D, C, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));
|
||||
else
|
||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));
|
||||
endgenerate
|
||||
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
|
||||
endmodule
|
||||
|
||||
module \$_DFFE_NN_ (input D, C, E, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
|
||||
else
|
||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
|
||||
endgenerate
|
||||
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
|
||||
endmodule
|
||||
|
||||
module \$_DFFE_PN_ (input D, C, E, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
|
||||
else
|
||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
|
||||
endgenerate
|
||||
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
|
||||
endmodule
|
||||
|
||||
module \$_DFFE_NP_ (input D, C, E, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
|
||||
else
|
||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
|
||||
endgenerate
|
||||
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
|
||||
endmodule
|
||||
|
||||
module \$_DFFE_PP_ (input D, C, E, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
|
||||
else
|
||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
|
||||
endgenerate
|
||||
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
|
||||
endmodule
|
||||
|
||||
module \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
|
||||
module \$_SDFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_SDFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_SDFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_SDFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
|
||||
module \$_DFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_DFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_DFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_DFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
|
||||
module \$_DFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_DFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_DFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_DFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
|
||||
module \$_SDFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_SDFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_SDFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_SDFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
|
||||
module \$_SDFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_SDFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_SDFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_SDFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
|
||||
module \$_ALDFF_NP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
|
||||
module \$_ALDFF_PP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
|
||||
|
||||
module \$_ALDFFE_NPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
|
||||
module \$_ALDFFE_NPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
|
||||
module \$_ALDFFE_PPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
|
||||
module \$_ALDFFE_PPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
|
||||
|
||||
`include "cells_ff.vh"
|
||||
`include "cells_io.vh"
|
||||
|
||||
`ifndef NO_LUT
|
||||
module \$lut (A, Y);
|
||||
parameter WIDTH = 0;
|
||||
parameter LUT = 0;
|
||||
|
||||
(* force_downto *)
|
||||
input [WIDTH-1:0] A;
|
||||
output Y;
|
||||
|
||||
generate
|
||||
if (WIDTH == 1) begin
|
||||
localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};
|
||||
LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),
|
||||
.A(1'b0), .B(1'b0), .C(1'b0), .D(A[0]));
|
||||
end else
|
||||
if (WIDTH == 2) begin
|
||||
localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};
|
||||
LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),
|
||||
.A(1'b0), .B(1'b0), .C(A[0]), .D(A[1]));
|
||||
end else
|
||||
if (WIDTH == 3) begin
|
||||
localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};
|
||||
LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),
|
||||
.A(1'b0), .B(A[0]), .C(A[1]), .D(A[2]));
|
||||
end else
|
||||
if (WIDTH == 4) begin
|
||||
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
`ifndef NO_PFUMUX
|
||||
end else
|
||||
if (WIDTH == 5) begin
|
||||
wire f0, f1;
|
||||
LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(Y));
|
||||
end else
|
||||
if (WIDTH == 6) begin
|
||||
wire f0, f1, f2, f3, g0, g1;
|
||||
LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
|
||||
LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
|
||||
PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));
|
||||
PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));
|
||||
L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y));
|
||||
end else
|
||||
if (WIDTH == 7) begin
|
||||
wire f0, f1, f2, f3, f4, f5, f6, f7, g0, g1, g2, g3, h0, h1;
|
||||
LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
|
||||
LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
|
||||
LUT4 #(.INIT(LUT[79:64])) lut4 (.Z(f4),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[95:80])) lut5 (.Z(f5),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
|
||||
LUT4 #(.INIT(LUT[111: 96])) lut6 (.Z(f6),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
|
||||
PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));
|
||||
PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));
|
||||
PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[4]), .Z(g2));
|
||||
PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[4]), .Z(g3));
|
||||
L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0));
|
||||
L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1));
|
||||
L6MUX21 mux7 (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y));
|
||||
`endif
|
||||
end else begin
|
||||
wire _TECHMAP_FAIL_ = 1;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
`endif
|
||||
|
|
@ -1,681 +0,0 @@
|
|||
// ---------------------------------------
|
||||
|
||||
(* abc9_lut=1, lib_whitebox *)
|
||||
module LUT4(input A, B, C, D, output Z);
|
||||
parameter [15:0] INIT = 16'h0000;
|
||||
wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
|
||||
wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
|
||||
wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
|
||||
assign Z = A ? s1[1] : s1[0];
|
||||
specify
|
||||
(A => Z) = 141;
|
||||
(B => Z) = 275;
|
||||
(C => Z) = 379;
|
||||
(D => Z) = 379;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// This is a placeholder for ABC9 to extract the area/delay
|
||||
// cost of 5-input LUTs and is not intended to be instantiated
|
||||
// LUT5 = 2x LUT4 + PFUMX
|
||||
(* abc9_lut=2 *)
|
||||
module \$__ABC9_LUT5 (input M0, D, C, B, A, output Z);
|
||||
specify
|
||||
(M0 => Z) = 151;
|
||||
(D => Z) = 239;
|
||||
(C => Z) = 373;
|
||||
(B => Z) = 477;
|
||||
(A => Z) = 477;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// This is a placeholder for ABC9 to extract the area/delay
|
||||
// of 6-input LUTs and is not intended to be instantiated
|
||||
// LUT6 = 2x LUT5 + MUX2
|
||||
(* abc9_lut=4 *)
|
||||
module \$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);
|
||||
specify
|
||||
(M1 => Z) = 148;
|
||||
(M0 => Z) = 292;
|
||||
(D => Z) = 380;
|
||||
(C => Z) = 514;
|
||||
(B => Z) = 618;
|
||||
(A => Z) = 618;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// This is a placeholder for ABC9 to extract the area/delay
|
||||
// of 7-input LUTs and is not intended to be instantiated
|
||||
// LUT7 = 2x LUT6 + MUX2
|
||||
(* abc9_lut=8 *)
|
||||
module \$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);
|
||||
specify
|
||||
(M2 => Z) = 148;
|
||||
(M1 => Z) = 289;
|
||||
(M0 => Z) = 433;
|
||||
(D => Z) = 521;
|
||||
(C => Z) = 655;
|
||||
(B => Z) = 759;
|
||||
(A => Z) = 759;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
(* abc9_box, lib_whitebox *)
|
||||
module L6MUX21 (input D0, D1, SD, output Z);
|
||||
assign Z = SD ? D1 : D0;
|
||||
specify
|
||||
(D0 => Z) = 140;
|
||||
(D1 => Z) = 141;
|
||||
(SD => Z) = 148;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
(* abc9_box, lib_whitebox *)
|
||||
module CCU2C(
|
||||
(* abc9_carry *)
|
||||
input CIN,
|
||||
input A0, B0, C0, D0, A1, B1, C1, D1,
|
||||
output S0, S1,
|
||||
(* abc9_carry *)
|
||||
output COUT
|
||||
);
|
||||
parameter [15:0] INIT0 = 16'h0000;
|
||||
parameter [15:0] INIT1 = 16'h0000;
|
||||
parameter INJECT1_0 = "YES";
|
||||
parameter INJECT1_1 = "YES";
|
||||
|
||||
// First half
|
||||
wire LUT4_0, LUT2_0;
|
||||
LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
|
||||
LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
|
||||
wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
|
||||
assign S0 = LUT4_0 ^ gated_cin_0;
|
||||
|
||||
wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
|
||||
wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
|
||||
|
||||
// Second half
|
||||
wire LUT4_1, LUT2_1;
|
||||
LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
|
||||
LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
|
||||
wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
|
||||
assign S1 = LUT4_1 ^ gated_cin_1;
|
||||
|
||||
wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
|
||||
assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
|
||||
|
||||
specify
|
||||
(A0 => S0) = 379;
|
||||
(B0 => S0) = 379;
|
||||
(C0 => S0) = 275;
|
||||
(D0 => S0) = 141;
|
||||
(CIN => S0) = 257;
|
||||
(A0 => S1) = 630;
|
||||
(B0 => S1) = 630;
|
||||
(C0 => S1) = 526;
|
||||
(D0 => S1) = 392;
|
||||
(A1 => S1) = 379;
|
||||
(B1 => S1) = 379;
|
||||
(C1 => S1) = 275;
|
||||
(D1 => S1) = 141;
|
||||
(CIN => S1) = 273;
|
||||
(A0 => COUT) = 516;
|
||||
(B0 => COUT) = 516;
|
||||
(C0 => COUT) = 412;
|
||||
(D0 => COUT) = 278;
|
||||
(A1 => COUT) = 516;
|
||||
(B1 => COUT) = 516;
|
||||
(C1 => COUT) = 412;
|
||||
(D1 => COUT) = 278;
|
||||
(CIN => COUT) = 43;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
|
||||
module TRELLIS_RAM16X2 (
|
||||
input DI0, DI1,
|
||||
input WAD0, WAD1, WAD2, WAD3,
|
||||
input WRE, WCK,
|
||||
input RAD0, RAD1, RAD2, RAD3,
|
||||
output DO0, DO1
|
||||
);
|
||||
parameter WCKMUX = "WCK";
|
||||
parameter WREMUX = "WRE";
|
||||
parameter INITVAL_0 = 16'h0000;
|
||||
parameter INITVAL_1 = 16'h0000;
|
||||
|
||||
reg [1:0] mem[15:0];
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 16; i = i + 1)
|
||||
mem[i] <= {INITVAL_1[i], INITVAL_0[i]};
|
||||
end
|
||||
|
||||
wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
|
||||
|
||||
reg muxwre;
|
||||
always @(*)
|
||||
case (WREMUX)
|
||||
"1": muxwre = 1'b1;
|
||||
"0": muxwre = 1'b0;
|
||||
"INV": muxwre = ~WRE;
|
||||
default: muxwre = WRE;
|
||||
endcase
|
||||
|
||||
|
||||
always @(posedge muxwck)
|
||||
if (muxwre)
|
||||
mem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};
|
||||
|
||||
assign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
(* abc9_box, lib_whitebox *)
|
||||
module PFUMX (input ALUT, BLUT, C0, output Z);
|
||||
assign Z = C0 ? ALUT : BLUT;
|
||||
specify
|
||||
(ALUT => Z) = 98;
|
||||
(BLUT => Z) = 98;
|
||||
(C0 => Z) = 151;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
(* abc9_box, lib_whitebox *)
|
||||
module TRELLIS_DPR16X4 (
|
||||
input [3:0] DI,
|
||||
input [3:0] WAD,
|
||||
input WRE,
|
||||
input WCK,
|
||||
input [3:0] RAD,
|
||||
output [3:0] DO
|
||||
);
|
||||
parameter WCKMUX = "WCK";
|
||||
parameter WREMUX = "WRE";
|
||||
parameter [63:0] INITVAL = 64'h0000000000000000;
|
||||
|
||||
reg [3:0] mem[15:0];
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 16; i = i + 1)
|
||||
mem[i] <= INITVAL[4*i +: 4];
|
||||
end
|
||||
|
||||
wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
|
||||
|
||||
reg muxwre;
|
||||
always @(*)
|
||||
case (WREMUX)
|
||||
"1": muxwre = 1'b1;
|
||||
"0": muxwre = 1'b0;
|
||||
"INV": muxwre = ~WRE;
|
||||
default: muxwre = WRE;
|
||||
endcase
|
||||
|
||||
always @(posedge muxwck)
|
||||
if (muxwre)
|
||||
mem[WAD] <= DI;
|
||||
|
||||
assign DO = mem[RAD];
|
||||
|
||||
specify
|
||||
// TODO
|
||||
(RAD *> DO) = 0;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
|
||||
(* abc9_box, lib_whitebox *)
|
||||
module DPR16X4C (
|
||||
input [3:0] DI,
|
||||
input WCK, WRE,
|
||||
input [3:0] RAD,
|
||||
input [3:0] WAD,
|
||||
output [3:0] DO
|
||||
);
|
||||
// For legacy Lattice compatibility, INITIVAL is a hex
|
||||
// string rather than a numeric parameter
|
||||
parameter INITVAL = "0x0000000000000000";
|
||||
|
||||
function [63:0] convert_initval;
|
||||
input [143:0] hex_initval;
|
||||
reg done;
|
||||
reg [63:0] temp;
|
||||
reg [7:0] char;
|
||||
integer i;
|
||||
begin
|
||||
done = 1'b0;
|
||||
temp = 0;
|
||||
for (i = 0; i < 16; i = i + 1) begin
|
||||
if (!done) begin
|
||||
char = hex_initval[8*i +: 8];
|
||||
if (char == "x") begin
|
||||
done = 1'b1;
|
||||
end else begin
|
||||
if (char >= "0" && char <= "9")
|
||||
temp[4*i +: 4] = char - "0";
|
||||
else if (char >= "A" && char <= "F")
|
||||
temp[4*i +: 4] = 10 + char - "A";
|
||||
else if (char >= "a" && char <= "f")
|
||||
temp[4*i +: 4] = 10 + char - "a";
|
||||
end
|
||||
end
|
||||
end
|
||||
convert_initval = temp;
|
||||
end
|
||||
endfunction
|
||||
|
||||
localparam conv_initval = convert_initval(INITVAL);
|
||||
|
||||
reg [3:0] ram[0:15];
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 15; i = i + 1) begin
|
||||
ram[i] <= conv_initval[4*i +: 4];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge WCK)
|
||||
if (WRE)
|
||||
ram[WAD] <= DI;
|
||||
|
||||
assign DO = ram[RAD];
|
||||
|
||||
specify
|
||||
// TODO
|
||||
(RAD *> DO) = 0;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
|
||||
(* lib_whitebox *)
|
||||
module LUT2(input A, B, output Z);
|
||||
parameter [3:0] INIT = 4'h0;
|
||||
wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0];
|
||||
assign Z = A ? s1[1] : s1[0];
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
|
||||
`ifdef YOSYS
|
||||
(* abc9_flop=(SRMODE != "ASYNC"), abc9_box=(SRMODE == "ASYNC"), lib_whitebox *)
|
||||
`endif
|
||||
module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
|
||||
parameter GSR = "ENABLED";
|
||||
parameter [127:0] CEMUX = "1";
|
||||
parameter CLKMUX = "CLK";
|
||||
parameter LSRMUX = "LSR";
|
||||
parameter SRMODE = "LSR_OVER_CE";
|
||||
parameter REGSET = "RESET";
|
||||
parameter [127:0] LSRMODE = "LSR";
|
||||
|
||||
wire muxce;
|
||||
generate
|
||||
case (CEMUX)
|
||||
"1": assign muxce = 1'b1;
|
||||
"0": assign muxce = 1'b0;
|
||||
"INV": assign muxce = ~CE;
|
||||
default: assign muxce = CE;
|
||||
endcase
|
||||
endgenerate
|
||||
|
||||
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
|
||||
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
|
||||
wire srval;
|
||||
generate
|
||||
if (LSRMODE == "PRLD")
|
||||
assign srval = M;
|
||||
else
|
||||
assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
|
||||
endgenerate
|
||||
|
||||
initial Q = srval;
|
||||
|
||||
generate
|
||||
if (SRMODE == "ASYNC") begin
|
||||
always @(posedge muxclk, posedge muxlsr)
|
||||
if (muxlsr)
|
||||
Q <= srval;
|
||||
else if (muxce)
|
||||
Q <= DI;
|
||||
end else begin
|
||||
always @(posedge muxclk)
|
||||
if (muxlsr)
|
||||
Q <= srval;
|
||||
else if (muxce)
|
||||
Q <= DI;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
specify
|
||||
$setup(DI, negedge CLK &&& CLKMUX == "INV", 0);
|
||||
$setup(CE, negedge CLK &&& CLKMUX == "INV", 0);
|
||||
$setup(LSR, negedge CLK &&& CLKMUX == "INV", 0);
|
||||
$setup(DI, posedge CLK &&& CLKMUX != "INV", 0);
|
||||
$setup(CE, posedge CLK &&& CLKMUX != "INV", 0);
|
||||
$setup(LSR, posedge CLK &&& CLKMUX != "INV", 0);
|
||||
`ifndef YOSYS
|
||||
if (SRMODE == "ASYNC" && muxlsr && CLKMUX == "INV") (negedge CLK => (Q : srval)) = 0;
|
||||
if (SRMODE == "ASYNC" && muxlsr && CLKMUX != "INV") (posedge CLK => (Q : srval)) = 0;
|
||||
`else
|
||||
if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path
|
||||
// but for facilitating a bypass box, let's pretend it's
|
||||
// a simple path
|
||||
`endif
|
||||
if (!muxlsr && muxce && CLKMUX == "INV") (negedge CLK => (Q : DI)) = 0;
|
||||
if (!muxlsr && muxce && CLKMUX != "INV") (posedge CLK => (Q : DI)) = 0;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
(* keep *)
|
||||
module TRELLIS_IO(
|
||||
(* iopad_external_pin *)
|
||||
inout B,
|
||||
input I,
|
||||
input T,
|
||||
output O
|
||||
);
|
||||
parameter DIR = "INPUT";
|
||||
reg T_pd;
|
||||
always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;
|
||||
|
||||
generate
|
||||
if (DIR == "INPUT") begin
|
||||
assign B = 1'bz;
|
||||
assign O = B;
|
||||
end else if (DIR == "OUTPUT") begin
|
||||
assign B = T_pd ? 1'bz : I;
|
||||
assign O = 1'bx;
|
||||
end else if (DIR == "BIDIR") begin
|
||||
assign B = T_pd ? 1'bz : I;
|
||||
assign O = B;
|
||||
end else begin
|
||||
ERROR_UNKNOWN_IO_MODE error();
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
|
||||
module INV(input A, output Z);
|
||||
assign Z = !A;
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
|
||||
module TRELLIS_COMB(
|
||||
input A, B, C, D, M,
|
||||
input FCI, F1, FXA, FXB,
|
||||
input WD,
|
||||
input WAD0, WAD1, WAD2, WAD3,
|
||||
input WRE, WCK,
|
||||
output F, FCO, OFX
|
||||
);
|
||||
parameter MODE = "LOGIC";
|
||||
parameter INITVAL = 16'h0;
|
||||
parameter CCU2_INJECT1 = "NO";
|
||||
parameter WREMUX = "WRE";
|
||||
parameter IS_Z1 = 1'b0;
|
||||
|
||||
generate
|
||||
if (MODE == "LOGIC") begin: mode_logic
|
||||
LUT4 #(.INIT(INITVAL)) lut4 (.A(A), .B(B), .C(C), .D(D), .Z(F));
|
||||
end else if (MODE == "CCU2") begin: mode_ccu2
|
||||
wire l4o, l2o;
|
||||
LUT4 #(.INIT(INITVAL)) lut4_0(.A(A), .B(B), .C(C), .D(D), .Z(l4o));
|
||||
LUT2 #(.INIT(INITVAL[3:0])) lut2_0(.A(A), .B(B), .Z(l2o));
|
||||
wire gated_cin_0 = (CCU2_INJECT1 == "YES") ? 1'b0 : FCI;
|
||||
assign F = l4o ^ gated_cin_0;
|
||||
wire gated_lut2_0 = (CCU2_INJECT1 == "YES") ? 1'b0 : l2o;
|
||||
wire FCO = (~l4o & gated_lut2_0) | (l4o & FCI);
|
||||
end else if (MODE == "DPRAM") begin: mode_dpram
|
||||
reg [15:0] ram = INITVAL;
|
||||
always @(posedge WCK)
|
||||
if (WRE)
|
||||
ram[{WAD3, WAD2, WAD1, WAD0}] <= WD;
|
||||
assign F = ram[{A, C, B, D}];
|
||||
end else begin
|
||||
$error("unsupported COMB mode %s", MODE);
|
||||
end
|
||||
|
||||
if (IS_Z1)
|
||||
L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M), .Z(OFX));
|
||||
else
|
||||
PFUMX lut5_mux (.ALUT(F1), .BLUT(F), .C0(M), .Z(OFX));
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DP16KD(
|
||||
input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
|
||||
input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,
|
||||
input CEA, OCEA, CLKA, WEA, RSTA,
|
||||
input CSA2, CSA1, CSA0,
|
||||
output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
|
||||
|
||||
input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
|
||||
input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,
|
||||
input CEB, OCEB, CLKB, WEB, RSTB,
|
||||
input CSB2, CSB1, CSB0,
|
||||
output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
|
||||
);
|
||||
parameter DATA_WIDTH_A = 18;
|
||||
parameter DATA_WIDTH_B = 18;
|
||||
|
||||
parameter REGMODE_A = "NOREG";
|
||||
parameter REGMODE_B = "NOREG";
|
||||
|
||||
parameter RESETMODE = "SYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
|
||||
parameter CSDECODE_A = "0b000";
|
||||
parameter CSDECODE_B = "0b000";
|
||||
|
||||
parameter WRITEMODE_A = "NORMAL";
|
||||
parameter WRITEMODE_B = "NORMAL";
|
||||
|
||||
parameter DIA17MUX = "DIA17";
|
||||
parameter DIA16MUX = "DIA16";
|
||||
parameter DIA15MUX = "DIA15";
|
||||
parameter DIA14MUX = "DIA14";
|
||||
parameter DIA13MUX = "DIA13";
|
||||
parameter DIA12MUX = "DIA12";
|
||||
parameter DIA11MUX = "DIA11";
|
||||
parameter DIA10MUX = "DIA10";
|
||||
parameter DIA9MUX = "DIA9";
|
||||
parameter DIA8MUX = "DIA8";
|
||||
parameter DIA7MUX = "DIA7";
|
||||
parameter DIA6MUX = "DIA6";
|
||||
parameter DIA5MUX = "DIA5";
|
||||
parameter DIA4MUX = "DIA4";
|
||||
parameter DIA3MUX = "DIA3";
|
||||
parameter DIA2MUX = "DIA2";
|
||||
parameter DIA1MUX = "DIA1";
|
||||
parameter DIA0MUX = "DIA0";
|
||||
parameter ADA13MUX = "ADA13";
|
||||
parameter ADA12MUX = "ADA12";
|
||||
parameter ADA11MUX = "ADA11";
|
||||
parameter ADA10MUX = "ADA10";
|
||||
parameter ADA9MUX = "ADA9";
|
||||
parameter ADA8MUX = "ADA8";
|
||||
parameter ADA7MUX = "ADA7";
|
||||
parameter ADA6MUX = "ADA6";
|
||||
parameter ADA5MUX = "ADA5";
|
||||
parameter ADA4MUX = "ADA4";
|
||||
parameter ADA3MUX = "ADA3";
|
||||
parameter ADA2MUX = "ADA2";
|
||||
parameter ADA1MUX = "ADA1";
|
||||
parameter ADA0MUX = "ADA0";
|
||||
parameter CEAMUX = "CEA";
|
||||
parameter OCEAMUX = "OCEA";
|
||||
parameter CLKAMUX = "CLKA";
|
||||
parameter WEAMUX = "WEA";
|
||||
parameter RSTAMUX = "RSTA";
|
||||
parameter CSA2MUX = "CSA2";
|
||||
parameter CSA1MUX = "CSA1";
|
||||
parameter CSA0MUX = "CSA0";
|
||||
parameter DOA17MUX = "DOA17";
|
||||
parameter DOA16MUX = "DOA16";
|
||||
parameter DOA15MUX = "DOA15";
|
||||
parameter DOA14MUX = "DOA14";
|
||||
parameter DOA13MUX = "DOA13";
|
||||
parameter DOA12MUX = "DOA12";
|
||||
parameter DOA11MUX = "DOA11";
|
||||
parameter DOA10MUX = "DOA10";
|
||||
parameter DOA9MUX = "DOA9";
|
||||
parameter DOA8MUX = "DOA8";
|
||||
parameter DOA7MUX = "DOA7";
|
||||
parameter DOA6MUX = "DOA6";
|
||||
parameter DOA5MUX = "DOA5";
|
||||
parameter DOA4MUX = "DOA4";
|
||||
parameter DOA3MUX = "DOA3";
|
||||
parameter DOA2MUX = "DOA2";
|
||||
parameter DOA1MUX = "DOA1";
|
||||
parameter DOA0MUX = "DOA0";
|
||||
parameter DIB17MUX = "DIB17";
|
||||
parameter DIB16MUX = "DIB16";
|
||||
parameter DIB15MUX = "DIB15";
|
||||
parameter DIB14MUX = "DIB14";
|
||||
parameter DIB13MUX = "DIB13";
|
||||
parameter DIB12MUX = "DIB12";
|
||||
parameter DIB11MUX = "DIB11";
|
||||
parameter DIB10MUX = "DIB10";
|
||||
parameter DIB9MUX = "DIB9";
|
||||
parameter DIB8MUX = "DIB8";
|
||||
parameter DIB7MUX = "DIB7";
|
||||
parameter DIB6MUX = "DIB6";
|
||||
parameter DIB5MUX = "DIB5";
|
||||
parameter DIB4MUX = "DIB4";
|
||||
parameter DIB3MUX = "DIB3";
|
||||
parameter DIB2MUX = "DIB2";
|
||||
parameter DIB1MUX = "DIB1";
|
||||
parameter DIB0MUX = "DIB0";
|
||||
parameter ADB13MUX = "ADB13";
|
||||
parameter ADB12MUX = "ADB12";
|
||||
parameter ADB11MUX = "ADB11";
|
||||
parameter ADB10MUX = "ADB10";
|
||||
parameter ADB9MUX = "ADB9";
|
||||
parameter ADB8MUX = "ADB8";
|
||||
parameter ADB7MUX = "ADB7";
|
||||
parameter ADB6MUX = "ADB6";
|
||||
parameter ADB5MUX = "ADB5";
|
||||
parameter ADB4MUX = "ADB4";
|
||||
parameter ADB3MUX = "ADB3";
|
||||
parameter ADB2MUX = "ADB2";
|
||||
parameter ADB1MUX = "ADB1";
|
||||
parameter ADB0MUX = "ADB0";
|
||||
parameter CEBMUX = "CEB";
|
||||
parameter OCEBMUX = "OCEB";
|
||||
parameter CLKBMUX = "CLKB";
|
||||
parameter WEBMUX = "WEB";
|
||||
parameter RSTBMUX = "RSTB";
|
||||
parameter CSB2MUX = "CSB2";
|
||||
parameter CSB1MUX = "CSB1";
|
||||
parameter CSB0MUX = "CSB0";
|
||||
parameter DOB17MUX = "DOB17";
|
||||
parameter DOB16MUX = "DOB16";
|
||||
parameter DOB15MUX = "DOB15";
|
||||
parameter DOB14MUX = "DOB14";
|
||||
parameter DOB13MUX = "DOB13";
|
||||
parameter DOB12MUX = "DOB12";
|
||||
parameter DOB11MUX = "DOB11";
|
||||
parameter DOB10MUX = "DOB10";
|
||||
parameter DOB9MUX = "DOB9";
|
||||
parameter DOB8MUX = "DOB8";
|
||||
parameter DOB7MUX = "DOB7";
|
||||
parameter DOB6MUX = "DOB6";
|
||||
parameter DOB5MUX = "DOB5";
|
||||
parameter DOB4MUX = "DOB4";
|
||||
parameter DOB3MUX = "DOB3";
|
||||
parameter DOB2MUX = "DOB2";
|
||||
parameter DOB1MUX = "DOB1";
|
||||
parameter DOB0MUX = "DOB0";
|
||||
|
||||
parameter WID = 0;
|
||||
|
||||
parameter GSR = "ENABLED";
|
||||
|
||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_DATA = "STATIC";
|
||||
endmodule
|
||||
|
||||
`ifndef NO_INCLUDES
|
||||
|
||||
`include "cells_ff.vh"
|
||||
`include "cells_io.vh"
|
||||
|
||||
`endif
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
|
||||
|
||||
parameter A_WIDTH = 18;
|
||||
parameter B_WIDTH = 18;
|
||||
parameter Y_WIDTH = 36;
|
||||
parameter A_SIGNED = 0;
|
||||
parameter B_SIGNED = 0;
|
||||
|
||||
MULT18X18D _TECHMAP_REPLACE_ (
|
||||
.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),
|
||||
.B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),
|
||||
.C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),
|
||||
.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0), .SIGNEDB(B_SIGNED ? 1'b1 : 1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0),
|
||||
|
||||
.P0(Y[0]), .P1(Y[1]), .P2(Y[2]), .P3(Y[3]), .P4(Y[4]), .P5(Y[5]), .P6(Y[6]), .P7(Y[7]), .P8(Y[8]), .P9(Y[9]), .P10(Y[10]), .P11(Y[11]), .P12(Y[12]), .P13(Y[13]), .P14(Y[14]), .P15(Y[15]), .P16(Y[16]), .P17(Y[17]), .P18(Y[18]), .P19(Y[19]), .P20(Y[20]), .P21(Y[21]), .P22(Y[22]), .P23(Y[23]), .P24(Y[24]), .P25(Y[25]), .P26(Y[26]), .P27(Y[27]), .P28(Y[28]), .P29(Y[29]), .P30(Y[30]), .P31(Y[31]), .P32(Y[32]), .P33(Y[33]), .P34(Y[34]), .P35(Y[35])
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
module \$_DLATCH_N_ (E, D, Q);
|
||||
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
|
||||
input E, D;
|
||||
output Q = !E ? D : Q;
|
||||
endmodule
|
||||
|
||||
module \$_DLATCH_P_ (E, D, Q);
|
||||
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
|
||||
input E, D;
|
||||
output Q = E ? D : Q;
|
||||
endmodule
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
ram distributed $__TRELLIS_DPR16X4_ {
|
||||
abits 4;
|
||||
width 4;
|
||||
cost 4;
|
||||
init any;
|
||||
prune_rom;
|
||||
port sw "W" {
|
||||
clock anyedge;
|
||||
}
|
||||
port ar "R" {
|
||||
}
|
||||
}
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
module $__TRELLIS_DPR16X4_(...);
|
||||
|
||||
parameter INIT = 64'bx;
|
||||
parameter PORT_W_CLK_POL = 1;
|
||||
|
||||
input PORT_W_CLK;
|
||||
input [3:0] PORT_W_ADDR;
|
||||
input [3:0] PORT_W_WR_DATA;
|
||||
input PORT_W_WR_EN;
|
||||
|
||||
input [3:0] PORT_R_ADDR;
|
||||
output [3:0] PORT_R_RD_DATA;
|
||||
|
||||
localparam WCKMUX = PORT_W_CLK_POL ? "WCK" : "INV";
|
||||
|
||||
TRELLIS_DPR16X4 #(
|
||||
.INITVAL(INIT),
|
||||
.WCKMUX(WCKMUX),
|
||||
.WREMUX("WRE")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.RAD(PORT_R_ADDR),
|
||||
.DO(PORT_R_RD_DATA),
|
||||
|
||||
.WAD(PORT_W_ADDR),
|
||||
.DI(PORT_W_WR_DATA),
|
||||
.WCK(PORT_W_CLK),
|
||||
.WRE(PORT_W_WR_EN)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,455 +0,0 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
|
||||
* Copyright (C) 2018 gatecat <gatecat@ds0.me>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "kernel/register.h"
|
||||
#include "kernel/celltypes.h"
|
||||
#include "kernel/rtlil.h"
|
||||
#include "kernel/log.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
struct SynthEcp5Pass : public ScriptPass
|
||||
{
|
||||
SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
|
||||
|
||||
void on_register() override
|
||||
{
|
||||
RTLIL::constpad["synth_ecp5.abc9.W"] = "300";
|
||||
}
|
||||
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" synth_ecp5 [options]\n");
|
||||
log("\n");
|
||||
log("This command runs synthesis for ECP5 FPGAs.\n");
|
||||
log("\n");
|
||||
log(" -top <module>\n");
|
||||
log(" use the specified module as top module\n");
|
||||
log("\n");
|
||||
log(" -blif <file>\n");
|
||||
log(" write the design to the specified BLIF file. writing of an output file\n");
|
||||
log(" is omitted if this parameter is not specified.\n");
|
||||
log("\n");
|
||||
log(" -edif <file>\n");
|
||||
log(" write the design to the specified EDIF file. writing of an output file\n");
|
||||
log(" is omitted if this parameter is not specified.\n");
|
||||
log("\n");
|
||||
log(" -json <file>\n");
|
||||
log(" write the design to the specified JSON file. writing of an output file\n");
|
||||
log(" is omitted if this parameter is not specified.\n");
|
||||
log("\n");
|
||||
log(" -run <from_label>:<to_label>\n");
|
||||
log(" only run the commands between the labels (see below). an empty\n");
|
||||
log(" from label is synonymous to 'begin', and empty to label is\n");
|
||||
log(" synonymous to the end of the command list.\n");
|
||||
log("\n");
|
||||
log(" -noflatten\n");
|
||||
log(" do not flatten design before synthesis\n");
|
||||
log("\n");
|
||||
log(" -dff\n");
|
||||
log(" run 'abc'/'abc9' with -dff option\n");
|
||||
log("\n");
|
||||
log(" -retime\n");
|
||||
log(" run 'abc' with '-dff -D 1' options\n");
|
||||
log("\n");
|
||||
log(" -noccu2\n");
|
||||
log(" do not use CCU2 cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nodffe\n");
|
||||
log(" do not use flipflops with CE in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nobram\n");
|
||||
log(" do not use block RAM cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nolutram\n");
|
||||
log(" do not use LUT RAM cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nowidelut\n");
|
||||
log(" do not use PFU muxes to implement LUTs larger than LUT4s\n");
|
||||
log("\n");
|
||||
log(" -asyncprld\n");
|
||||
log(" use async PRLD mode to implement ALDFF (EXPERIMENTAL)\n");
|
||||
log("\n");
|
||||
log(" -abc2\n");
|
||||
log(" run two passes of 'abc' for slightly improved logic density\n");
|
||||
log("\n");
|
||||
log(" -noabc9\n");
|
||||
log(" disable use of new ABC9 flow\n");
|
||||
log("\n");
|
||||
log(" -vpr\n");
|
||||
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
|
||||
log(" (this feature is experimental and incomplete)\n");
|
||||
log("\n");
|
||||
log(" -iopad\n");
|
||||
log(" insert IO buffers\n");
|
||||
log("\n");
|
||||
log(" -nodsp\n");
|
||||
log(" do not map multipliers to MULT18X18D\n");
|
||||
log("\n");
|
||||
log(" -no-rw-check\n");
|
||||
log(" marks all recognized read ports as \"return don't-care value on\n");
|
||||
log(" read/write collision\" (same result as setting the no_rw_check\n");
|
||||
log(" attribute on all memories).\n");
|
||||
log("\n");
|
||||
log("\n");
|
||||
log("The following commands are executed by this synthesis command:\n");
|
||||
help_script();
|
||||
log("\n");
|
||||
}
|
||||
|
||||
string top_opt, blif_file, edif_file, json_file;
|
||||
bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, vpr, no_rw_check;
|
||||
|
||||
void clear_flags() override
|
||||
{
|
||||
top_opt = "-auto-top";
|
||||
blif_file = "";
|
||||
edif_file = "";
|
||||
json_file = "";
|
||||
noccu2 = false;
|
||||
nodffe = false;
|
||||
nobram = false;
|
||||
nolutram = false;
|
||||
nowidelut = false;
|
||||
asyncprld = false;
|
||||
flatten = true;
|
||||
dff = false;
|
||||
retime = false;
|
||||
abc2 = false;
|
||||
vpr = false;
|
||||
abc9 = true;
|
||||
iopad = false;
|
||||
nodsp = false;
|
||||
no_rw_check = false;
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
string run_from, run_to;
|
||||
clear_flags();
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
{
|
||||
if (args[argidx] == "-top" && argidx+1 < args.size()) {
|
||||
top_opt = "-top " + args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-blif" && argidx+1 < args.size()) {
|
||||
blif_file = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-edif" && argidx+1 < args.size()) {
|
||||
edif_file = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-json" && argidx+1 < args.size()) {
|
||||
json_file = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-run" && argidx+1 < args.size()) {
|
||||
size_t pos = args[argidx+1].find(':');
|
||||
if (pos == std::string::npos)
|
||||
break;
|
||||
run_from = args[++argidx].substr(0, pos);
|
||||
run_to = args[argidx].substr(pos+1);
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-flatten") {
|
||||
flatten = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-noflatten") {
|
||||
flatten = false;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-dff") {
|
||||
dff = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-retime") {
|
||||
retime = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-noccu2") {
|
||||
noccu2 = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nodffe") {
|
||||
nodffe = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nobram") {
|
||||
nobram = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-asyncprld") {
|
||||
asyncprld = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
|
||||
nolutram = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nowidelut" || /*deprecated alias*/ args[argidx] == "-nomux") {
|
||||
nowidelut = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-abc2") {
|
||||
abc2 = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-vpr") {
|
||||
vpr = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-abc9") {
|
||||
// removed, ABC9 is on by default.
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-noabc9") {
|
||||
abc9 = false;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-iopad") {
|
||||
iopad = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nodsp") {
|
||||
nodsp = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-no-rw-check") {
|
||||
no_rw_check = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
if (!design->full_selection())
|
||||
log_cmd_error("This command only operates on fully selected designs!\n");
|
||||
|
||||
if (abc9 && retime)
|
||||
log_cmd_error("-retime option not currently compatible with -abc9!\n");
|
||||
|
||||
log_header(design, "Executing SYNTH_ECP5 pass.\n");
|
||||
log_push();
|
||||
|
||||
run_script(design, run_from, run_to);
|
||||
|
||||
log_pop();
|
||||
}
|
||||
|
||||
void script() override
|
||||
{
|
||||
std::string no_rw_check_opt = "";
|
||||
if (no_rw_check)
|
||||
no_rw_check_opt = " -no-rw-check";
|
||||
if (help_mode)
|
||||
no_rw_check_opt = " [-no-rw-check]";
|
||||
|
||||
if (check_label("begin"))
|
||||
{
|
||||
run("read_verilog -lib -specify +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
|
||||
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
|
||||
}
|
||||
|
||||
if (check_label("coarse"))
|
||||
{
|
||||
run("proc");
|
||||
if (flatten || help_mode)
|
||||
run("flatten");
|
||||
run("tribuf -logic");
|
||||
run("deminout");
|
||||
run("opt_expr");
|
||||
run("opt_clean");
|
||||
run("check");
|
||||
run("opt -nodffe -nosdff");
|
||||
run("fsm");
|
||||
run("opt");
|
||||
run("wreduce");
|
||||
run("peepopt");
|
||||
run("opt_clean");
|
||||
run("share");
|
||||
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
|
||||
run("opt_expr");
|
||||
run("opt_clean");
|
||||
if (!nodsp) {
|
||||
run("techmap -map +/mul2dsp.v -map +/ecp5/dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18", "(unless -nodsp)");
|
||||
run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)");
|
||||
}
|
||||
run("alumacc");
|
||||
run("opt");
|
||||
run("memory -nomap" + no_rw_check_opt);
|
||||
run("opt_clean");
|
||||
}
|
||||
|
||||
if (check_label("map_ram"))
|
||||
{
|
||||
std::string args = "";
|
||||
if (nobram)
|
||||
args += " -no-auto-block";
|
||||
if (nolutram)
|
||||
args += " -no-auto-distributed";
|
||||
if (help_mode)
|
||||
args += " [-no-auto-block] [-no-auto-distributed]";
|
||||
run("memory_libmap -lib +/ecp5/lutrams.txt -lib +/ecp5/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
|
||||
run("techmap -map +/ecp5/lutrams_map.v -map +/ecp5/brams_map.v");
|
||||
}
|
||||
|
||||
if (check_label("map_ffram"))
|
||||
{
|
||||
run("opt -fast -mux_undef -undriven -fine");
|
||||
run("memory_map");
|
||||
run("opt -undriven -fine");
|
||||
}
|
||||
|
||||
if (check_label("map_gates"))
|
||||
{
|
||||
if (noccu2)
|
||||
run("techmap");
|
||||
else
|
||||
run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
|
||||
if (help_mode || iopad) {
|
||||
run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(only if '-iopad')");
|
||||
run("attrmvcp -attr src -attr LOC t:OB %x:+[O] t:OBZ %x:+[O] t:BB %x:+[B]");
|
||||
run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]");
|
||||
}
|
||||
run("opt -fast");
|
||||
if (retime || help_mode)
|
||||
run("abc -dff -D 1", "(only if -retime)");
|
||||
}
|
||||
|
||||
if (check_label("map_ffs"))
|
||||
{
|
||||
run("opt_clean");
|
||||
std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r";
|
||||
if (help_mode) {
|
||||
dfflegalize_args += " [-cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r]";
|
||||
} else if (!nodffe) {
|
||||
dfflegalize_args += " -cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r";
|
||||
}
|
||||
if (help_mode) {
|
||||
dfflegalize_args += " [-cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x] [-cell $_DLATCH_?_ x]";
|
||||
} else if (asyncprld) {
|
||||
dfflegalize_args += " -cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x";
|
||||
} else {
|
||||
dfflegalize_args += " -cell $_DLATCH_?_ x";
|
||||
}
|
||||
run("dfflegalize" + dfflegalize_args, "($_ALDFF_*_ only if -asyncprld, $_DLATCH_* only if not -asyncprld, $_*DFFE_* only if not -nodffe)");
|
||||
if ((abc9 && dff) || help_mode)
|
||||
run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff)");
|
||||
run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
|
||||
run("opt_expr -undriven -mux_undef");
|
||||
run("simplemap");
|
||||
run("lattice_gsr");
|
||||
run("attrmvcp -copy -attr syn_useioff");
|
||||
run("opt_clean");
|
||||
}
|
||||
|
||||
if (check_label("map_luts"))
|
||||
{
|
||||
if (abc2 || help_mode)
|
||||
run("abc", " (only if -abc2)");
|
||||
if (!asyncprld || help_mode)
|
||||
run("techmap -map +/ecp5/latches_map.v", "(skip if -asyncprld)");
|
||||
|
||||
if (abc9) {
|
||||
std::string abc9_opts;
|
||||
if (nowidelut)
|
||||
abc9_opts += " -maxlut 4";
|
||||
std::string k = "synth_ecp5.abc9.W";
|
||||
if (active_design && active_design->scratchpad.count(k))
|
||||
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
|
||||
else
|
||||
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
|
||||
if (nowidelut)
|
||||
abc9_opts += " -maxlut 4";
|
||||
if (dff)
|
||||
abc9_opts += " -dff";
|
||||
run("abc9" + abc9_opts);
|
||||
} else {
|
||||
std::string abc_args = " -dress";
|
||||
if (nowidelut)
|
||||
abc_args += " -lut 4";
|
||||
else
|
||||
abc_args += " -lut 4:7";
|
||||
if (dff)
|
||||
abc_args += " -dff";
|
||||
run("abc" + abc_args);
|
||||
}
|
||||
run("clean");
|
||||
}
|
||||
|
||||
if (check_label("map_cells"))
|
||||
{
|
||||
if (help_mode)
|
||||
run("techmap -map +/ecp5/cells_map.v", "(skip if -vpr)");
|
||||
else if (!vpr)
|
||||
run("techmap -map +/ecp5/cells_map.v");
|
||||
run("opt_lut_ins -tech lattice");
|
||||
run("clean");
|
||||
}
|
||||
|
||||
if (check_label("check"))
|
||||
{
|
||||
run("autoname");
|
||||
run("hierarchy -check");
|
||||
run("stat");
|
||||
run("check -noinit");
|
||||
run("blackbox =A:whitebox");
|
||||
}
|
||||
|
||||
if (check_label("blif"))
|
||||
{
|
||||
if (!blif_file.empty() || help_mode) {
|
||||
if (vpr || help_mode) {
|
||||
run(stringf("opt_clean -purge"),
|
||||
" (vpr mode)");
|
||||
run(stringf("write_blif -attr -cname -conn -param %s",
|
||||
help_mode ? "<file-name>" : blif_file.c_str()),
|
||||
" (vpr mode)");
|
||||
}
|
||||
if (!vpr)
|
||||
run(stringf("write_blif -gates -attr -param %s",
|
||||
help_mode ? "<file-name>" : blif_file.c_str()),
|
||||
" (non-vpr mode)");
|
||||
}
|
||||
}
|
||||
|
||||
if (check_label("edif"))
|
||||
{
|
||||
if (!edif_file.empty() || help_mode)
|
||||
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
|
||||
}
|
||||
|
||||
if (check_label("json"))
|
||||
{
|
||||
if (!json_file.empty() || help_mode)
|
||||
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
|
||||
}
|
||||
}
|
||||
} SynthEcp5Pass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
Loading…
Reference in a new issue