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Bmux unq

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This commit is contained in:
Akash Levy 2024-11-04 12:03:53 -08:00
parent 2d929f2e99
commit 1eb577120e
1 changed files with 19 additions and 0 deletions
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19
passes/techmap/bmuxmap.cc
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@ -36,10 +36,14 @@ struct BmuxmapPass : public Pass {
log(" -pmux\n"); log(" -pmux\n");
log(" transform to $pmux instead of $mux cells.\n"); log(" transform to $pmux instead of $mux cells.\n");
log("\n"); log("\n");
log(" -fewunq\n");
log(" only transform $bmux cells that have few unique A bits.\n");
log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
{ {
bool pmux_mode = false; bool pmux_mode = false;
bool fewunq_mode = false;
log_header(design, "Executing BMUXMAP pass.\n"); log_header(design, "Executing BMUXMAP pass.\n");
@ -49,6 +53,10 @@ struct BmuxmapPass : public Pass {
pmux_mode = true; pmux_mode = true;
continue; continue;
} }
if (args[argidx] == "-fewunq") {
fewunq_mode = true;
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
@ -59,6 +67,17 @@ struct BmuxmapPass : public Pass {
if (cell->type != ID($bmux)) if (cell->type != ID($bmux))
continue; continue;
if (fewunq_mode) {
SigSpec data = cell->getPort(ID::A);
SigMap sigmap(module);
pool<SigBit> unqbits;
for (auto bit : data)
if (bit.wire != nullptr)
unqbits.insert(sigmap(bit));
if (GetSize(unqbits) > GetSize(data)/2)
continue;
}
SigSpec sel = cell->getPort(ID::S); SigSpec sel = cell->getPort(ID::S);
SigSpec data = cell->getPort(ID::A); SigSpec data = cell->getPort(ID::A);
int width = GetSize(cell->getPort(ID::Y)); int width = GetSize(cell->getPort(ID::Y));