From 1eb577120e10c61317349bb2402ea137cb2f0db5 Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Mon, 4 Nov 2024 12:03:53 -0800
Subject: [PATCH] Bmux unq

---
 passes/techmap/bmuxmap.cc | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/passes/techmap/bmuxmap.cc b/passes/techmap/bmuxmap.cc
index 069cc1aa7..1495e6247 100644
--- a/passes/techmap/bmuxmap.cc
+++ b/passes/techmap/bmuxmap.cc
@@ -36,10 +36,14 @@ struct BmuxmapPass : public Pass {
 		log("    -pmux\n");
 		log("        transform to $pmux instead of $mux cells.\n");
 		log("\n");
+		log("    -fewunq\n");
+		log("        only transform $bmux cells that have few unique A bits.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		bool pmux_mode = false;
+		bool fewunq_mode = false;
 
 		log_header(design, "Executing BMUXMAP pass.\n");
 
@@ -49,6 +53,10 @@ struct BmuxmapPass : public Pass {
 				pmux_mode = true;
 				continue;
 			}
+			if (args[argidx] == "-fewunq") {
+				fewunq_mode = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -58,6 +66,17 @@ struct BmuxmapPass : public Pass {
 		{
 			if (cell->type != ID($bmux))
 				continue;
+			
+			if (fewunq_mode) {
+				SigSpec data = cell->getPort(ID::A);
+				SigMap sigmap(module);
+				pool<SigBit> unqbits;
+				for (auto bit : data)
+					if (bit.wire != nullptr)
+						unqbits.insert(sigmap(bit));
+				if (GetSize(unqbits) > GetSize(data)/2)
+					continue;
+			}
 
 			SigSpec sel = cell->getPort(ID::S);
 			SigSpec data = cell->getPort(ID::A);