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https://github.com/YosysHQ/yosys
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Merge 0635df4ee5
into 733487e730
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commit
1dd51a158a
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@ -771,8 +771,6 @@ struct AST_INTERNAL::ProcessGenerator
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if (node->type == AST_CONSTANT && node->is_string) {
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arg.type = VerilogFmtArg::STRING;
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arg.str = node->bitsAsConst().decode_string();
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// and in case this will be used as an argument...
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arg.sig = node->bitsAsConst();
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arg.signed_ = false;
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} else if (node->type == AST_IDENTIFIER && node->str == "$time") {
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arg.type = VerilogFmtArg::TIME;
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@ -378,7 +378,7 @@ void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_lik
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}
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case VerilogFmtArg::STRING: {
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if (arg == args.begin() || !sformat_like) {
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if ((arg == args.begin() || !sformat_like) && !arg->str.empty()) {
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const auto fmtarg = arg;
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const std::string &fmt = fmtarg->str;
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FmtPart part = {};
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@ -407,8 +407,19 @@ void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_lik
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if (++arg == args.end()) {
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log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with fewer arguments than the format specifiers in argument %zu require.\n", task_name.c_str(), fmtarg - args.begin() + 1);
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}
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part.sig = arg->sig;
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part.signed_ = arg->signed_;
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switch (arg->type) {
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case VerilogFmtArg::STRING:
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part.sig = arg->str.empty() ? arg->sig : Const(arg->str);
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part.signed_ = false;
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break;
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case VerilogFmtArg::INTEGER:
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part.sig = arg->sig;
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part.signed_ = arg->signed_;
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break;
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default:
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// requires `%t`/`%T` which is enforced later on
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break;
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}
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for (; i < fmt.size(); i++) {
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if (fmt[i] == '-') {
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@ -472,9 +483,10 @@ void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_lik
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}
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break;
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}
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if (i == fmt.size()) {
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if (i == fmt.size())
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log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1);
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}
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if (arg->type == VerilogFmtArg::TIME && part.type != FmtPart::VLOG_TIME)
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log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with format character `%c' in argument %zu, but the argument is $time or $realtime.\n", task_name.c_str(), fmt[i], fmtarg - args.begin() + 1);
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if (part.padding == '\0') {
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if (has_leading_zero && part.justify == FmtPart::RIGHT) {
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15
kernel/fmt.h
15
kernel/fmt.h
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@ -26,6 +26,17 @@ YOSYS_NAMESPACE_BEGIN
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// Verilog format argument, such as the arguments in:
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// $display("foo %d bar %01x", 4'b0, $signed(2'b11))
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//
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// Argument mapping:
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//
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// (1) quoted string literal -> STRING, literal in `str`
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// (2) type `string` or unpacked `byte` array -> STRING, value in `sig` (SystemVerilog extension)
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// (3) `$time` `$realtime` -> TIME, `realtime` selects between the two
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// (4) any other expression -> INTEGER, value in `sig`
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//
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// We need to distinguish (1) and (2) because that influences interpretation
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// of escape characters (only interpreted in (1)).
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//
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struct VerilogFmtArg {
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enum {
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STRING = 0,
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@ -40,8 +51,10 @@ struct VerilogFmtArg {
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// STRING type
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std::string str;
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// INTEGER type
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// INTEGER/STRING type
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RTLIL::SigSpec sig;
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// INTEGER
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bool signed_ = false;
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// TIME type
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