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fmt: Extend string handling for SystemVerilog

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This makes for a distinction between a string argument from a quoted
literal, and a string argument from a variable or other expression.
This commit is contained in:
Martin Povišer 2024-02-08 15:03:38 +01:00
parent 71235f9b48
commit 0635df4ee5
3 changed files with 28 additions and 6 deletions
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2
frontends/ast/genrtlil.cc
View file

@ -771,8 +771,6 @@ struct AST_INTERNAL::ProcessGenerator
if (node->type == AST_CONSTANT && node->is_string) {
arg.type = VerilogFmtArg::STRING;
arg.str = node->bitsAsConst().decode_string();
// and in case this will be used as an argument...
arg.sig = node->bitsAsConst();
arg.signed_ = false;
} else if (node->type == AST_IDENTIFIER && node->str == "$time") {
arg.type = VerilogFmtArg::TIME;

17
kernel/fmt.cc
View file

@ -337,7 +337,7 @@ void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_lik
}
case VerilogFmtArg::STRING: {
if (arg == args.begin() || !sformat_like) {
if ((arg == args.begin() || !sformat_like) && !arg->str.empty()) {
const auto fmtarg = arg;
const std::string &fmt = fmtarg->str;
FmtPart part = {};
@ -366,8 +366,19 @@ void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_lik
if (++arg == args.end()) {
log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with fewer arguments than the format specifiers in argument %zu require.\n", task_name.c_str(), fmtarg - args.begin() + 1);
}
part.sig = arg->sig;
part.signed_ = arg->signed_;
switch (arg->type) {
case VerilogFmtArg::STRING:
part.sig = arg->str.empty() ? arg->sig : Const(arg->str);
part.signed_ = false;
break;
case VerilogFmtArg::INTEGER:
part.sig = arg->sig;
part.signed_ = arg->signed_;
break;
default:
// requires `%t`/`%T` which is enforced later on
break;
}
for (; i < fmt.size(); i++) {
if (fmt[i] == '-') {

15
kernel/fmt.h
View file

@ -26,6 +26,17 @@ YOSYS_NAMESPACE_BEGIN
// Verilog format argument, such as the arguments in:
// $display("foo %d bar %01x", 4'b0, $signed(2'b11))
//
// Argument mapping:
//
// (1) quoted string literal -> STRING, literal in `str`
// (2) type `string` or unpacked `byte` array -> STRING, value in `sig` (SystemVerilog extension)
// (3) `$time` `$realtime` -> TIME, `realtime` selects between the two
// (4) any other expression -> INTEGER, value in `sig`
//
// We need to distinguish (1) and (2) because that influences interpretation
// of escape characters (only interpreted in (1)).
//
struct VerilogFmtArg {
enum {
STRING = 0,
@ -40,8 +51,10 @@ struct VerilogFmtArg {
// STRING type
std::string str;
// INTEGER type
// INTEGER/STRING type
RTLIL::SigSpec sig;
// INTEGER
bool signed_ = false;
// TIME type