Merge pull request #1046 from bogdanvuk/master

Optimizing DFFs whose initial value prevents their value from changing

tests/opt/opt_ff_sat.v

@@ -0,0 +1,12 @@
+module top (
+	input clk,
+	output reg [7:0] cnt
+);
+	initial cnt = 0;
+	always @(posedge clk) begin
+		if (cnt < 20)
+			cnt <= cnt + 1;
+		else
+			cnt <= 0;
+	end
+endmodule

tests/opt/opt_ff_sat.ys

@@ -0,0 +1,5 @@
+read_verilog opt_ff_sat.v
+prep -flatten
+opt_rmdff -sat
+synth
+select -assert-count 5 t:$_DFF_P_