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yosys/tests/opt/opt_ff_sat.ys
Clifford Wolf 2454ad99bf Refactor "opt_rmdff -sat"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 13:44:21 +02:00

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read_verilog opt_ff_sat.v
prep -flatten
opt_rmdff -sat
synth
select -assert-count 5 t:$_DFF_P_