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add morphCell instead of type assignments, test_cell passes for all cells

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This commit is contained in:
Emil J. Tywoniak 2024-06-20 23:41:09 +02:00
parent d2107a9ee4
commit 1be8f8023a
33 changed files with 129 additions and 99 deletions
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16
techlibs/coolrunner2/coolrunner2_sop.cc
View file

@ -170,14 +170,14 @@ struct Coolrunner2SopPass : public Pass {
if (has_invert)
{
auto cell = std::get<0>(x);
if (cell->type == ID(FDCP)) cell->type = ID(FDCP_N);
else if (cell->type == ID(FDCP_N)) cell->type = ID(FDCP);
else if (cell->type == ID(FTCP)) cell->type = ID(FTCP_N);
else if (cell->type == ID(FTCP_N)) cell->type = ID(FTCP);
else if (cell->type == ID(FDCPE)) cell->type = ID(FDCPE_N);
else if (cell->type == ID(FDCPE_N)) cell->type = ID(FDCPE);
else if (cell->type == ID(LDCP)) cell->type = ID(LDCP_N);
else if (cell->type == ID(LDCP_N)) cell->type = ID(LDCP);
if (cell->type == ID(FDCP)) cell = cell->module->morphCell(ID(FDCP_N), cell);
else if (cell->type == ID(FDCP_N)) cell = cell->module->morphCell(ID(FDCP), cell);
else if (cell->type == ID(FTCP)) cell = cell->module->morphCell(ID(FTCP_N), cell);
else if (cell->type == ID(FTCP_N)) cell = cell->module->morphCell(ID(FTCP), cell);
else if (cell->type == ID(FDCPE)) cell = cell->module->morphCell(ID(FDCPE_N), cell);
else if (cell->type == ID(FDCPE_N)) cell = cell->module->morphCell(ID(FDCPE), cell);
else if (cell->type == ID(LDCP)) cell = cell->module->morphCell(ID(LDCP_N), cell);
else if (cell->type == ID(LDCP_N)) cell = cell->module->morphCell(ID(LDCP), cell);
else log_assert(!"Internal error! Bad cell type!");
}
}

4
techlibs/greenpak4/greenpak4_dffinv.cc
View file

@ -81,9 +81,9 @@ void invert_gp_dff(Cell *cell, bool invert_input)
}
if(cell_type_latch)
cell->type = stringf("\\GP_DLATCH%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
cell = cell->module->morphCell(stringf("\\GP_DLATCH%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : ""), cell);
else
cell->type = stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
cell = cell->module->morphCell(stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : ""), cell);
log("Merged %s inverter into cell %s.%s: %s -> %s\n", invert_input ? "input" : "output",
log_id(cell->module), log_id(cell), cell_type.c_str()+1, log_id(cell->type));

4
techlibs/ice40/ice40_opt.cc
View file

@ -138,7 +138,7 @@ static void run_ice40_opts(Module *module)
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = ID($lut);
cell = cell->module->morphCell(ID($lut), cell);
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)));
cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) });
cell->setPort(ID::Y, cell->getPort(ID::O));
@ -177,7 +177,7 @@ static void run_ice40_opts(Module *module)
module->design->scratchpad_set_bool("opt.did_something", true);
log("Mapping SB_LUT4 cell %s.%s back to logic.\n", log_id(module), log_id(cell));
cell->type = ID($lut);
cell = cell->module->morphCell(ID($lut), cell);
cell->setParam(ID::WIDTH, 4);
cell->setParam(ID::LUT, cell->getParam(ID(LUT_INIT)));
cell->unsetParam(ID(LUT_INIT));

2
techlibs/quicklogic/ql_bram_types.cc
View file

@ -154,7 +154,7 @@ struct QlBramTypesPass : public Pass {
type += "nonsplit";
}
cell->type = RTLIL::escape_id(type);
cell = cell->module->morphCell(RTLIL::escape_id(type), cell);
log_debug("Changed type of memory cell %s to %s\n", log_id(cell->name), log_id(cell->type));
}
}

2
techlibs/quicklogic/ql_dsp_io_regs.cc
View file

@ -127,7 +127,7 @@ struct QlDspIORegs : public Pass {
}
// Set new type name
cell->type = RTLIL::IdString(new_type);
cell = cell->module->morphCell(RTLIL::IdString(new_type), cell);
std::vector<std::string> ports2del;