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reconsidering unset

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This commit is contained in:
Emil J. Tywoniak 2024-06-20 16:43:45 +02:00
parent 76102f0bc5
commit d2107a9ee4
4 changed files with 17 additions and 15 deletions
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1
kernel/rtlil.cc
View file

@ -2458,6 +2458,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
{
log_assert(other);
RTLIL::Cell *cell = addCell(name, other->type);
cell->connections_ = other->connections_;
cell->parameters = other->parameters;

19
kernel/rtlil.h
View file

@ -2030,14 +2030,11 @@ public:
return !operator==(other);
}
int count(const RTLIL::IdString& portname) const {
log("count this %d\n", this);
try {
parent->getPort(portname);
} catch (const std::out_of_range& e) {
log("count 0\n");
return 0;
}
log("count 1\n");
return 1;
}
size_t size() const {
@ -2270,13 +2267,15 @@ public:
throw std::out_of_range("FakeParams::size()");
}
}
// TODO check
void unsetPort(const RTLIL::IdString& portname) {
if (is_legacy())
legacy->unsetPort(portname);
setPort(portname, SigSpec());
try {
setPort(portname, SigSpec());
} catch (const std::out_of_range& e) {}
}
void setParam(const RTLIL::IdString &paramname, RTLIL::Const value);
// TODO is this reasonable at all?
const RTLIL::Const& getParam(const RTLIL::IdString &paramname) const;
RTLIL::Const& getMutParam(const RTLIL::IdString &paramname);
bool hasParam(const RTLIL::IdString &paramname) const {
@ -2288,18 +2287,16 @@ public:
throw std::out_of_range("FakeParams::size()");
}
}
// TODO check
void unsetParam(const RTLIL::IdString& paramname) {
if (is_legacy())
legacy->unsetParam(paramname);
setPort(paramname, Const());
try {
setPort(paramname, Const());
} catch (const std::out_of_range& e) {}
}
template<typename T>
void rewrite_sigspecs2(T &functor) {
// for(auto it = connections_.begin(); it != connections_.end(); ++it) {
// auto& thing = *it;
// functor(it.second);
// }
// TODO fix!!!
for (auto it : connections_)
functor(it.second);
}

8
passes/opt/opt_expr.cc
View file

@ -408,6 +408,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
for (auto cell : module->cells())
if (design->selected(module, cell) && cell->type[0] == '$') {
log("%s\n", cell->name.c_str());
log_cell(cell, "inner ");
if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) &&
GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::A));
@ -2305,6 +2307,9 @@ struct OptExprPass : public Pass {
CellTypes ct(design);
for (auto module : design->selected_modules())
{
for (auto cell : module->cells()) {
log_cell(cell, "start ");
}
log("Optimizing module %s.\n", log_id(module));
if (undriven) {
@ -2313,6 +2318,9 @@ struct OptExprPass : public Pass {
if (did_something)
design->scratchpad_set_bool("opt.did_something", true);
}
for (auto cell : module->cells()) {
log_cell(cell, "mid ");
}
do {
do {

4
passes/techmap/alumacc.cc
View file

@ -240,12 +240,8 @@ struct AlumaccWorker
for (int i = 0; i < GetSize(n->macc.ports); i++)
{
log("ports: size %d\n", n->macc.ports.size());
auto &port = n->macc.ports[i];
log("ports 2: size %d\n", port.in_b.size());
log("uuh: count %d\n", sig_macc.count(port.in_a));
log("%s\n", log_signal(port.in_a));
if (GetSize(port.in_b) > 0 || sig_macc.count(port.in_a) == 0)
continue;