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https://github.com/YosysHQ/yosys
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add morphCell instead of type assignments, test_cell passes for all cells
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parent
d2107a9ee4
commit
1be8f8023a
33 changed files with 129 additions and 99 deletions
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@ -331,16 +331,18 @@ struct TechmapWorker
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else
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apply_prefix(cell->name, c_name);
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auto type = tpl_cell->type;
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RTLIL::Cell *c = module->addCell(c_name, tpl_cell);
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design->select(module, c);
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if (c->type.begins_with("\\$"))
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c->type = c->type.substr(1);
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if (c->type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype)) {
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c->type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype));
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if (type.begins_with("\\$"))
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type = type.substr(1);
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if (type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype)) {
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type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype));
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c->attributes.erase(ID::techmap_chtype);
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}
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c = module->morphCell(type, c);
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vector<IdString> autopurge_ports;
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@ -508,7 +510,7 @@ struct TechmapWorker
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if (!extmapper_name.empty())
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{
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cell->type = cell_type;
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cell = cell->module->morphCell(cell_type, cell);
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if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
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{
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@ -570,7 +572,7 @@ struct TechmapWorker
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}
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}
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cell->type = extmapper_module->name;
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cell = cell->module->morphCell(extmapper_module->name, cell);
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cell->parameters.clear();
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if (!extern_mode || in_recursion) {
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@ -937,14 +939,14 @@ struct TechmapWorker
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for (auto cell : m->cells()) {
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if (cell->type.begins_with("\\$"))
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cell->type = cell->type.substr(1);
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cell = cell->module->morphCell(cell->type.substr(1), cell);
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}
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module_queue.insert(m);
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}
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log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
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cell->type = m_name;
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cell = cell->module->morphCell(m_name, cell);
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cell->parameters.clear();
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}
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else
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