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add morphCell instead of type assignments, test_cell passes for all cells

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This commit is contained in:
Emil J. Tywoniak 2024-06-20 23:41:09 +02:00
parent d2107a9ee4
commit 1be8f8023a
33 changed files with 129 additions and 99 deletions
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6
passes/techmap/abc9_ops.cc
View file

@ -195,7 +195,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
// If derived_type is present in unmap_design, it means that it was processed previously, but found to be incompatible -- e.g. if
// it contained a non-zero initial state. In this case, continue to replace the cell type/parameters so that it has the same properties
// as a compatible type, yet will be safely unmapped later
cell->type = derived_type;
cell = cell->module->morphCell(derived_type, cell);
cell->parameters.clear();
unused_derived.erase(derived_type);
}
@ -255,7 +255,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
}
}
cell->type = derived_type;
cell = cell->module->morphCell(derived_type, cell);
cell->parameters.clear();
unused_derived.erase(derived_type);
}
@ -1344,7 +1344,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
RTLIL::Module* box_module = design->module(existing_cell->type);
log_assert(existing_cell->parameters.empty());
log_assert(mapped_cell->type == stringf("$__boxid%d", box_module->attributes.at(ID::abc9_box_id).as_int()));
mapped_cell->type = existing_cell->type;
mapped_cell = mapped_cell->module->morphCell(existing_cell->type, mapped_cell);
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
cell->parameters = existing_cell->parameters;

2
passes/techmap/extract_counter.cc
View file

@ -628,7 +628,7 @@ void counter_worker(
cell->unsetParam(ID::Y_WIDTH);
//Change the cell type
cell->type = ID($__COUNT_);
cell = cell->module->morphCell(ID($__COUNT_), cell);
//Hook up resets
if(extract.has_reset)

2
passes/techmap/shregmap.cc
View file

@ -332,7 +332,7 @@ struct ShregmapWorker
if (opts.ffe) first_cell->setParam(ID(ENPOL), param_enpol);
}
first_cell->type = shreg_cell_type_str;
first_cell = first_cell->module->morphCell(shreg_cell_type_str, first_cell);
first_cell->setPort(q_port, last_cell->getPort(q_port));
first_cell->setParam(ID::DEPTH, depth);

20
passes/techmap/techmap.cc
View file

@ -331,16 +331,18 @@ struct TechmapWorker
else
apply_prefix(cell->name, c_name);
auto type = tpl_cell->type;
RTLIL::Cell *c = module->addCell(c_name, tpl_cell);
design->select(module, c);
if (c->type.begins_with("\\$"))
c->type = c->type.substr(1);
if (c->type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype)) {
c->type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype));
if (type.begins_with("\\$"))
type = type.substr(1);
if (type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype)) {
type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype));
c->attributes.erase(ID::techmap_chtype);
}
c = module->morphCell(type, c);
vector<IdString> autopurge_ports;
@ -508,7 +510,7 @@ struct TechmapWorker
if (!extmapper_name.empty())
{
cell->type = cell_type;
cell = cell->module->morphCell(cell_type, cell);
if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
{
@ -570,7 +572,7 @@ struct TechmapWorker
}
}
cell->type = extmapper_module->name;
cell = cell->module->morphCell(extmapper_module->name, cell);
cell->parameters.clear();
if (!extern_mode || in_recursion) {
@ -937,14 +939,14 @@ struct TechmapWorker
for (auto cell : m->cells()) {
if (cell->type.begins_with("\\$"))
cell->type = cell->type.substr(1);
cell = cell->module->morphCell(cell->type.substr(1), cell);
}
module_queue.insert(m);
}
log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
cell->type = m_name;
cell = cell->module->morphCell(m_name, cell);
cell->parameters.clear();
}
else

4
passes/techmap/tribuf.cc
View file

@ -86,7 +86,7 @@ struct TribufWorker {
cell->setPort(en_port, cell->getPort(ID::S));
cell->unsetPort(ID::B);
cell->unsetPort(ID::S);
cell->type = tri_type;
cell = cell->module->morphCell(tri_type, cell);
tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
module->design->scratchpad_set_bool("tribuf.added_something", true);
continue;
@ -96,7 +96,7 @@ struct TribufWorker {
cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(ID::S)));
cell->unsetPort(ID::B);
cell->unsetPort(ID::S);
cell->type = tri_type;
cell = cell->module->morphCell(tri_type, cell);
tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
module->design->scratchpad_set_bool("tribuf.added_something", true);
continue;