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add morphCell instead of type assignments, test_cell passes for all cells

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This commit is contained in:
Emil J. Tywoniak 2024-06-20 23:41:09 +02:00
parent d2107a9ee4
commit 1be8f8023a
33 changed files with 129 additions and 99 deletions
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2
passes/opt/muxpack.cc
View file

@ -269,7 +269,7 @@ struct MuxpackWorker
mux_count += cases;
pmux_count += 1;
first_cell->type = ID($pmux);
first_cell = first_cell->module->morphCell(ID($pmux), first_cell);
SigSpec b_sig = first_cell->getPort(ID::B);
SigSpec s_sig = first_cell->getPort(ID::S);

4
passes/opt/opt_demorgan.cc
View file

@ -155,9 +155,9 @@ void demorgan_worker(
//Change the cell type
if(cell->type == ID($reduce_and))
cell->type = ID($reduce_or);
cell = m->morphCell(ID($reduce_or), cell);
else if(cell->type == ID($reduce_or))
cell->type = ID($reduce_and);
cell = m->morphCell(ID($reduce_and), cell);
//don't change XOR
//Add an inverter to the output

43
passes/opt/opt_expr.cc
View file

@ -125,7 +125,6 @@ void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell,
log_debug("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
cell->type.c_str(), cell->name.c_str(), info.c_str(),
module->name.c_str(), log_signal(Y), log_signal(out_val));
// log_cell(cell);
assign_map.add(Y, out_val);
module->connect(Y, out_val);
module->remove(cell);
@ -341,7 +340,7 @@ void handle_clkpol_celltype_swap(Cell *cell, string type1, string type2, IdStrin
log_id(port), log_id(cell->type), log_id(cell), log_id(cell->module),
log_signal(sig), log_signal(invert_map.at(sig)));
cell->setPort(port, (invert_map.at(sig)));
cell->type = cell->type == type1 ? type2 : type1;
cell = cell->module->morphCell(cell->type == type1 ? type2 : type1, cell);
}
}
}
@ -408,8 +407,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
for (auto cell : module->cells())
if (design->selected(module, cell) && cell->type[0] == '$') {
log("%s\n", cell->name.c_str());
log_cell(cell, "inner ");
if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) &&
GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::A));
@ -642,7 +639,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover("opt.opt_expr.reduce_xnor_not");
log_debug("Replacing %s cell `%s' in module `%s' with $not cell.\n",
log_id(cell->type), log_id(cell->name), log_id(module));
cell->type = ID($not);
cell = cell->module->morphCell(ID($not), cell);
did_something = true;
} else {
cover("opt.opt_expr.unary_buffer");
@ -1169,7 +1166,7 @@ skip_fine_alu:
if (input.match("01 ")) ACTION_DO(ID::Y, input.extract(0, 1));
if (input.match("10 ")) {
cover("opt.opt_expr.mux_to_inv");
cell->type = ID($_NOT_);
cell = cell->module->morphCell(ID($_NOT_), cell);
cell->setPort(ID::A, input.extract(0, 1));
cell->unsetPort(ID::B);
cell->unsetPort(ID::S);
@ -1273,7 +1270,7 @@ skip_fine_alu:
} else {
cover_list("opt.opt_expr.eqneq.isnot", "$eq", "$ne", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
cell->type = ID($not);
cell = cell->module->morphCell(ID($not), cell);
cell->parameters.erase(ID::B_WIDTH);
cell->parameters.erase(ID::B_SIGNED);
cell->unsetPort(ID::B);
@ -1289,7 +1286,7 @@ skip_fine_alu:
cover_list("opt.opt_expr.eqneq.cmpzero", "$eq", "$ne", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell),
log_id(module), cell->type == ID($eq) ? "$logic_not" : "$reduce_bool");
cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool);
cell = cell->module->morphCell(cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool), cell);
if (assign_map(cell->getPort(ID::A)).is_fully_zero()) {
cell->setPort(ID::A, cell->getPort(ID::B));
cell->setParam(ID::A_SIGNED, cell->getParam(ID::B_SIGNED));
@ -1437,7 +1434,7 @@ skip_fine_alu:
cell->setParam(ID::A_SIGNED, cell->getParam(ID::B_SIGNED));
}
cell->type = arith_inverse ? ID($neg) : ID($pos);
cell = cell->module->morphCell(arith_inverse ? ID($neg) : ID($pos), cell);
cell->unsetPort(ID::B);
cell->parameters.erase(ID::B_WIDTH);
cell->parameters.erase(ID::B_SIGNED);
@ -1469,9 +1466,9 @@ skip_identity:
cell->parameters[ID::Y_WIDTH] = width;
cell->parameters[ID::A_SIGNED] = 0;
cell->parameters.erase(ID::WIDTH);
cell->type = ID($not);
cell = cell->module->morphCell(ID($not), cell);
} else
cell->type = ID($_NOT_);
cell = cell->module->morphCell(ID($_NOT_), cell);
did_something = true;
goto next_cell;
}
@ -1489,9 +1486,9 @@ skip_identity:
cell->parameters[ID::A_SIGNED] = 0;
cell->parameters[ID::B_SIGNED] = 0;
cell->parameters.erase(ID::WIDTH);
cell->type = ID($and);
cell = cell->module->morphCell(ID($and), cell);
} else
cell->type = ID($_AND_);
cell = cell->module->morphCell(ID($_AND_), cell);
did_something = true;
goto next_cell;
}
@ -1509,9 +1506,9 @@ skip_identity:
cell->parameters[ID::A_SIGNED] = 0;
cell->parameters[ID::B_SIGNED] = 0;
cell->parameters.erase(ID::WIDTH);
cell->type = ID($or);
cell = cell->module->morphCell(ID($or), cell);
} else
cell->type = ID($_OR_);
cell = cell->module->morphCell(ID($_OR_), cell);
did_something = true;
goto next_cell;
}
@ -1557,10 +1554,10 @@ skip_identity:
cell->setPort(ID::B, new_b);
cell->setPort(ID::S, new_s);
if (new_s.size() > 1) {
cell->type = ID($pmux);
cell = cell->module->morphCell(ID($pmux), cell);
cell->parameters[ID::S_WIDTH] = new_s.size();
} else {
cell->type = ID($mux);
cell = cell->module->morphCell(ID($mux), cell);
cell->parameters.erase(ID::S_WIDTH);
}
did_something = true;
@ -1733,7 +1730,7 @@ skip_identity:
Const new_b = exp;
cell->type = ID($shl);
cell = cell->module->morphCell(ID($shl), cell);
cell->parameters[ID::B_WIDTH] = GetSize(new_b);
cell->parameters[ID::B_SIGNED] = false;
cell->setPort(ID::B, new_b);
@ -1824,7 +1821,7 @@ skip_identity:
Const new_b = exp;
cell->type = ID($sshr);
cell = cell->module->morphCell(ID($sshr), cell);
cell->parameters[ID::B_WIDTH] = GetSize(new_b);
cell->parameters[ID::B_SIGNED] = false;
cell->setPort(ID::B, new_b);
@ -1873,7 +1870,7 @@ skip_identity:
if (b_signed || exp == 0)
new_b.push_back(State::S0);
cell->type = ID($and);
cell = cell->module->morphCell(ID($and), cell);
cell->parameters[ID::B_WIDTH] = GetSize(new_b);
cell->setPort(ID::B, new_b);
cell->check();
@ -2307,9 +2304,6 @@ struct OptExprPass : public Pass {
CellTypes ct(design);
for (auto module : design->selected_modules())
{
for (auto cell : module->cells()) {
log_cell(cell, "start ");
}
log("Optimizing module %s.\n", log_id(module));
if (undriven) {
@ -2318,9 +2312,6 @@ struct OptExprPass : public Pass {
if (did_something)
design->scratchpad_set_bool("opt.did_something", true);
}
for (auto cell : module->cells()) {
log_cell(cell, "mid ");
}
do {
do {

12
passes/opt/opt_lut_ins.cc
View file

@ -244,17 +244,17 @@ struct OptLutInsPass : public Pass {
else
log_assert(GetSize(new_inputs) <= 4);
if (GetSize(new_inputs) == 1)
cell->type = ID(LUT1);
cell = cell->module->morphCell(ID(LUT1), cell);
else if (GetSize(new_inputs) == 2)
cell->type = ID(LUT2);
cell = cell->module->morphCell(ID(LUT2), cell);
else if (GetSize(new_inputs) == 3)
cell->type = ID(LUT3);
cell = cell->module->morphCell(ID(LUT3), cell);
else if (GetSize(new_inputs) == 4)
cell->type = ID(LUT4);
cell = cell->module->morphCell(ID(LUT4), cell);
else if (GetSize(new_inputs) == 5)
cell->type = ID(LUT5);
cell = cell->module->morphCell(ID(LUT5), cell);
else if (GetSize(new_inputs) == 6)
cell->type = ID(LUT6);
cell = cell->module->morphCell(ID(LUT6), cell);
else
log_assert(0);
cell->unsetPort(ID(I0));

2
passes/opt/opt_muxtree.cc
View file

@ -259,7 +259,7 @@ struct OptMuxtreeWorker
mi.cell->setPort(ID::B, new_sig_b);
mi.cell->setPort(ID::S, new_sig_s);
if (GetSize(new_sig_s) == 1) {
mi.cell->type = ID($mux);
mi.cell = mi.cell->module->morphCell(ID($mux), mi.cell);
mi.cell->parameters.erase(ID::S_WIDTH);
} else {
mi.cell->parameters[ID::S_WIDTH] = RTLIL::Const(GetSize(new_sig_s));

4
passes/opt/opt_reduce.cc
View file

@ -160,7 +160,7 @@ struct OptReduceWorker
if (new_sig_s.size() > 1) {
cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size());
} else {
cell->type = ID($mux);
cell = cell->module->morphCell(ID($mux), cell);
cell->parameters.erase(ID::S_WIDTH);
}
}
@ -228,7 +228,7 @@ struct OptReduceWorker
if (new_sig_s.size() == 1)
{
cell->type = ID($mux);
cell = cell->module->morphCell(ID($mux), cell);
cell->setPort(ID::A, new_sig_a.extract(0, width));
cell->setPort(ID::B, new_sig_a.extract(width, width));
cell->setPort(ID::S, new_sig_s);