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https://github.com/YosysHQ/yosys
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add morphCell instead of type assignments, test_cell passes for all cells
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parent
d2107a9ee4
commit
1be8f8023a
33 changed files with 129 additions and 99 deletions
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@ -2434,7 +2434,6 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
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cell->type = type;
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if (RTLIL::Cell::is_legacy_type(type)) {
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cell->legacy = new RTLIL::OldCell;
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cell->legacy->name = name;
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cell->legacy->type = type;
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cell->legacy->module = this;
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log_assert(this);
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@ -2466,6 +2465,32 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
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return cell;
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}
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// Swap cell for a new one with a different type, keeping everything else
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// Throws if their types don't allow it
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RTLIL::Cell *RTLIL::Module::morphCell(RTLIL::IdString type, RTLIL::Cell *old)
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{
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// if (old->is_legacy() && Cell::is_legacy_type(type)) {
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// old->type = type;
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// return old;
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// }
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// TODO xtrace
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if (yosys_xtrace) {
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log("#X# Morphing %s.%s from type %s to %s\n", log_id(this), log_id(old), log_id(old->type), log_id(type));
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log_backtrace("-X- ", yosys_xtrace-1);
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}
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log_assert(old);
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cells_.erase(old->name);
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RTLIL::Cell *new_cell = addCell(old->name, type);
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new_cell->connections_ = old->connections_.as_dict();
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new_cell->parameters = old->parameters.as_dict();
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new_cell->attributes = old->attributes;
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new_cell->name = old->name;
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log_assert(refcount_cells_ == 0);
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cells_[new_cell->name] = new_cell;
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delete old;
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return new_cell;
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}
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RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memory *other)
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{
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RTLIL::Memory *mem = new RTLIL::Memory;
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