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add morphCell instead of type assignments, test_cell passes for all cells

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This commit is contained in:
Emil J. Tywoniak 2024-06-20 23:41:09 +02:00
parent d2107a9ee4
commit 1be8f8023a
33 changed files with 129 additions and 99 deletions
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8
kernel/mem.cc
View file

@ -125,7 +125,7 @@ void Mem::emit() {
memid = NEW_ID;
cell = module->addCell(memid, ID($mem_v2));
}
cell->type = ID($mem_v2);
cell = cell->module->morphCell(ID($mem_v2), cell);
cell->attributes = attributes;
cell->parameters[ID::MEMID] = Const(memid.str());
cell->parameters[ID::WIDTH] = Const(width);
@ -280,7 +280,7 @@ void Mem::emit() {
for (auto &port : rd_ports) {
if (!port.cell)
port.cell = module->addCell(NEW_ID, ID($memrd_v2));
port.cell->type = ID($memrd_v2);
port.cell = cell->module->morphCell(ID($memrd_v2), cell);
port.cell->attributes = port.attributes;
port.cell->parameters[ID::MEMID] = memid.str();
port.cell->parameters[ID::ABITS] = GetSize(port.addr);
@ -305,7 +305,7 @@ void Mem::emit() {
for (auto &port : wr_ports) {
if (!port.cell)
port.cell = module->addCell(NEW_ID, ID($memwr_v2));
port.cell->type = ID($memwr_v2);
port.cell = cell->module->morphCell(ID($memwr_v2), cell);
port.cell->attributes = port.attributes;
if (port.cell->parameters.count(ID::PRIORITY))
port.cell->parameters.erase(ID::PRIORITY);
@ -327,7 +327,7 @@ void Mem::emit() {
if (!init.cell)
init.cell = module->addCell(NEW_ID, v2 ? ID($meminit_v2) : ID($meminit));
else
init.cell->type = v2 ? ID($meminit_v2) : ID($meminit);
init.cell = cell->module->morphCell(v2 ? ID($meminit_v2) : ID($meminit), cell);
init.cell->attributes = init.attributes;
init.cell->parameters[ID::MEMID] = memid.str();
init.cell->parameters[ID::ABITS] = GetSize(init.addr);

27
kernel/rtlil.cc
View file

@ -2434,7 +2434,6 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
cell->type = type;
if (RTLIL::Cell::is_legacy_type(type)) {
cell->legacy = new RTLIL::OldCell;
cell->legacy->name = name;
cell->legacy->type = type;
cell->legacy->module = this;
log_assert(this);
@ -2466,6 +2465,32 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
return cell;
}
// Swap cell for a new one with a different type, keeping everything else
// Throws if their types don't allow it
RTLIL::Cell *RTLIL::Module::morphCell(RTLIL::IdString type, RTLIL::Cell *old)
{
// if (old->is_legacy() && Cell::is_legacy_type(type)) {
// old->type = type;
// return old;
// }
// TODO xtrace
if (yosys_xtrace) {
log("#X# Morphing %s.%s from type %s to %s\n", log_id(this), log_id(old), log_id(old->type), log_id(type));
log_backtrace("-X- ", yosys_xtrace-1);
}
log_assert(old);
cells_.erase(old->name);
RTLIL::Cell *new_cell = addCell(old->name, type);
new_cell->connections_ = old->connections_.as_dict();
new_cell->parameters = old->parameters.as_dict();
new_cell->attributes = old->attributes;
new_cell->name = old->name;
log_assert(refcount_cells_ == 0);
cells_[new_cell->name] = new_cell;
delete old;
return new_cell;
}
RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memory *other)
{
RTLIL::Memory *mem = new RTLIL::Memory;

17
kernel/rtlil.h
View file

@ -1276,6 +1276,8 @@ public:
RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
RTLIL::Cell *morphCell(RTLIL::IdString type, RTLIL::Cell *old);
RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);
RTLIL::Process *addProcess(RTLIL::IdString name);
@ -1559,6 +1561,7 @@ struct RTLIL::OldCell
protected:
// use module->addCell() and module->remove() to create or destroy cells
// also see morphCell
friend struct RTLIL::Module;
friend struct RTLIL::Cell;
OldCell();
@ -1711,8 +1714,10 @@ public:
return parent->getMutParam(name);
}
void operator=(dict<IdString, Const> from) {
if (parent->is_legacy())
if (parent->is_legacy()) {
parent->legacy->parameters = from;
return;
}
if (parent->type == ID($not)) {
parent->not_.params_from_dict(from);
@ -1991,7 +1996,7 @@ public:
throw std::out_of_range("Cell::getParam()");
}
}
void operator=(const FakeConns& from) {
void operator=(const FakeConns& from) { // TODO check warning
log_assert(parent->type == from.parent->type);
if (parent->is_legacy()) {
@ -2269,8 +2274,10 @@ public:
}
// TODO check
void unsetPort(const RTLIL::IdString& portname) {
if (is_legacy())
if (is_legacy()) {
legacy->unsetPort(portname);
return;
}
try {
setPort(portname, SigSpec());
} catch (const std::out_of_range& e) {}
@ -2289,8 +2296,10 @@ public:
}
// TODO check
void unsetParam(const RTLIL::IdString& paramname) {
if (is_legacy())
if (is_legacy()) {
legacy->unsetParam(paramname);
return;
}
try {
setPort(paramname, Const());
} catch (const std::out_of_range& e) {}