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simplify: simplify

This commit is contained in:
Emil J. Tywoniak 2025-08-08 12:31:40 +02:00
parent 581b9684a2
commit 1a4dd18c5f

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@ -2180,14 +2180,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// use ProcessGenerator for always blocks
case AST_ALWAYS: {
auto always = this->clone();
ProcessGenerator generator(std::move(always));
ProcessGenerator generator(this->clone());
ignoreThisSignalsInInitial.append(generator.outputSignals);
} break;
case AST_INITIAL: {
auto always = this->clone();
ProcessGenerator generator(std::move(always), ignoreThisSignalsInInitial);
ProcessGenerator generator(this->clone(), ignoreThisSignalsInInitial);
} break;
case AST_TECALL: {