From 1a4dd18c5f747332e1ca58032ef04c88b6d96401 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 8 Aug 2025 12:31:40 +0200
Subject: [PATCH] simplify: simplify

---
 frontends/ast/genrtlil.cc | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 0002f6308..b53fa7a44 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -2180,14 +2180,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 	// use ProcessGenerator for always blocks
 	case AST_ALWAYS: {
-			auto always = this->clone();
-			ProcessGenerator generator(std::move(always));
+			ProcessGenerator generator(this->clone());
 			ignoreThisSignalsInInitial.append(generator.outputSignals);
 		} break;
 
 	case AST_INITIAL: {
 			auto always = this->clone();
-			ProcessGenerator generator(std::move(always), ignoreThisSignalsInInitial);
+			ProcessGenerator generator(this->clone(), ignoreThisSignalsInInitial);
 		} break;
 
 	case AST_TECALL: {