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intel_alm: Add multiply signedness to cells

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Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
This commit is contained in:
Dan Ravensloft 2020-08-26 18:44:48 +01:00 • committed by Marcelina Kościelnicka
parent 4f2b78e19a
commit 1a07b330f8
7 changed files with 147 additions and 16 deletions
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51
techlibs/intel_alm/common/dsp_sim.v
View file

@ -1,38 +1,83 @@
(* abc9_box *)
module MISTRAL_MUL27X27(input [26:0] A, input [26:0] B, output [53:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
(A *> Y) = 3732;
(B *> Y) = 3928;
endspecify
assign Y = $signed(A) * $signed(B);
wire [53:0] A_, B_;
if (A_SIGNED)
assign A_ = $signed(A);
else
assign A_ = $unsigned(A);
if (B_SIGNED)
assign B_ = $signed(B);
else
assign B_ = $unsigned(B);
assign Y = A_ * B_;
endmodule
(* abc9_box *)
module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
(A *> Y) = 3180;
(B *> Y) = 3982;
endspecify
assign Y = $signed(A) * $signed(B);
wire [35:0] A_, B_;
if (A_SIGNED)
assign A_ = $signed(A);
else
assign A_ = $unsigned(A);
if (B_SIGNED)
assign B_ = $signed(B);
else
assign B_ = $unsigned(B);
assign Y = A_ * B_;
endmodule
(* abc9_box *)
module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
(A *> Y) = 2818;
(B *> Y) = 3051;
endspecify
assign Y = $signed(A) * $signed(B);
wire [17:0] A_, B_;
if (A_SIGNED)
assign A_ = $signed(A);
else
assign A_ = $unsigned(A);
if (B_SIGNED)
assign B_ = $signed(B);
else
assign B_ = $unsigned(B);
assign Y = A_ * B_;
endmodule