diff --git a/tests/arch/quicklogic/qlf_k6n10f/mux.ys b/tests/arch/quicklogic/qlf_k6n10f/mux.ys
index 40b8dba06..60df06b69 100644
--- a/tests/arch/quicklogic/qlf_k6n10f/mux.ys
+++ b/tests/arch/quicklogic/qlf_k6n10f/mux.ys
@@ -34,6 +34,6 @@ proc
 equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 5 t:$lut r:WIDTH=6 %i # OOT flow does 2
+select -assert-max 5 t:$lut r:WIDTH=6 %i # OOT flow does 2
 select -assert-count 0 t:$lut r:WIDTH=3 %i # and here 1
 select -assert-none t:$lut r:WIDTH=6 r:WIDTH=3 %u %i %% t:* %D