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Don't adjust naming on imported cells. Add $ for each pass

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This commit is contained in:
Akash Levy 2024-05-19 15:02:40 -07:00
parent 8086e132fb
commit 187737b86a
3 changed files with 4 additions and 7 deletions
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7
frontends/verific/verific.cc
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@ -16,7 +16,7 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
* *
*/ */
#define YOSYS_ENABLE_VERIFIC
#include "kernel/yosys.h" #include "kernel/yosys.h"
#include "kernel/sigtools.h" #include "kernel/sigtools.h"
#include "kernel/celltypes.h" #include "kernel/celltypes.h"
@ -208,10 +208,7 @@ bool is_blackbox(Netlist *nl)
RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj) RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
{ {
std::string s = stringf("$imp$%s", obj->Name()); std::string s = stringf("$%s", obj->Name());
// if (obj->Linefile())
// s += stringf("$%s:%d.%d-%d.%d", RTLIL::encode_filename(LineFile::GetFileName(obj->Linefile())).c_str(), obj->Linefile()->GetLeftLine(), obj->Linefile()->GetLeftCol(), obj->Linefile()->GetRightLine(), obj->Linefile()->GetRightCol());
s += stringf("$%d", autoidx++);
return s; return s;
} }

2
kernel/ff.cc
View file

@ -263,7 +263,7 @@ FfData::FfData(FfInitVals *initvals, Cell *cell_) : FfData(cell_->module, initva
} }
FfData FfData::slice(const std::vector<int> &bits) { FfData FfData::slice(const std::vector<int> &bits) {
FfData res(module, initvals, NEW_ID); FfData res(module, initvals, IdString("$" + name.str()));
res.sig_clk = sig_clk; res.sig_clk = sig_clk;
res.sig_ce = sig_ce; res.sig_ce = sig_ce;
res.sig_aload = sig_aload; res.sig_aload = sig_aload;

2
passes/opt/wreduce.cc
View file

@ -458,7 +458,7 @@ struct WreduceWorker
continue; continue;
log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w)); log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w));
Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits); Wire *nw = module->addWire(IdString("$" + w->name.str()), GetSize(w) - unused_top_bits);
module->connect(nw, SigSpec(w).extract(0, GetSize(nw))); module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
module->swap_names(w, nw); module->swap_names(w, nw);
} }