From 187737b86a7ce4acb753a576fc2ced03ff0260b5 Mon Sep 17 00:00:00 2001
From: Akash Levy <akashlevy@gmail.com>
Date: Sun, 19 May 2024 15:02:40 -0700
Subject: [PATCH] Don't adjust naming on imported cells. Add $ for each pass

---
 frontends/verific/verific.cc | 7 ++-----
 kernel/ff.cc                 | 2 +-
 passes/opt/wreduce.cc        | 2 +-
 3 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 72ddbed38..c2b412dd3 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -16,7 +16,7 @@
  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
  */
-
+#define YOSYS_ENABLE_VERIFIC
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
 #include "kernel/celltypes.h"
@@ -208,10 +208,7 @@ bool is_blackbox(Netlist *nl)
 
 RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
 {
-	std::string s = stringf("$imp$%s", obj->Name());
-	// if (obj->Linefile())
-	//   s += stringf("$%s:%d.%d-%d.%d", RTLIL::encode_filename(LineFile::GetFileName(obj->Linefile())).c_str(), obj->Linefile()->GetLeftLine(), obj->Linefile()->GetLeftCol(), obj->Linefile()->GetRightLine(), obj->Linefile()->GetRightCol());
-	s += stringf("$%d", autoidx++);
+	std::string s = stringf("$%s", obj->Name());
 	return s;
 }
 
diff --git a/kernel/ff.cc b/kernel/ff.cc
index 697ba7342..d5094cad5 100644
--- a/kernel/ff.cc
+++ b/kernel/ff.cc
@@ -263,7 +263,7 @@ FfData::FfData(FfInitVals *initvals, Cell *cell_) : FfData(cell_->module, initva
 }
 
 FfData FfData::slice(const std::vector<int> &bits) {
-	FfData res(module, initvals, NEW_ID);
+	FfData res(module, initvals, IdString("$" + name.str()));
 	res.sig_clk = sig_clk;
 	res.sig_ce = sig_ce;
 	res.sig_aload = sig_aload;
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 87a5cb56d..f0e19e893 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -458,7 +458,7 @@ struct WreduceWorker
 				continue;
 
 			log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w));
-			Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits);
+			Wire *nw = module->addWire(IdString("$" + w->name.str()), GetSize(w) - unused_top_bits);
 			module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
 			module->swap_names(w, nw);
 		}