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Merge pull request #4614 from georgerennie/george/opt_reduce_cell_width

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opt_reduce: keep at least one input to $reduce_or/and cells
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Emil J 2024-11-20 13:33:04 +01:00 committed by GitHub
parent 88abc4c20f 0572f8806f
commit 18459b4b09
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2 changed files with 17 additions and 0 deletions
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3
passes/opt/opt_reduce.cc
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@ -89,6 +89,9 @@ struct OptReduceWorker
RTLIL::SigSpec new_sig_a(new_sig_a_bits); RTLIL::SigSpec new_sig_a(new_sig_a_bits);
new_sig_a.sort_and_unify(); new_sig_a.sort_and_unify();
if (GetSize(new_sig_a) == 0)
new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1;
if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) { if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
did_something = true; did_something = true;

14
tests/opt/opt_reduce_andor.ys Normal file
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@ -0,0 +1,14 @@
# Check that opt_reduce doesn't produce zero width $reduce_or/$reduce_and,
read_verilog <<EOT
module reduce_const(output wire o, output wire a);
wire [3:0] zero = 4'b0000;
wire [3:0] ones = 4'b1111;
assign o = |zero;
assign a = &ones;
endmodule
EOT
equiv_opt -assert opt_reduce
design -load postopt
select -assert-none r:A_WIDTH=0