mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-24 01:25:33 +00:00
opt_merge: fix trivial binary regression
This commit is contained in:
parent
8903740147
commit
176faae7c9
2 changed files with 13 additions and 1 deletions
|
@ -95,7 +95,6 @@ struct OptMergeWorker
|
|||
};
|
||||
std::sort(inputs.begin(), inputs.end());
|
||||
h = hash_ops<std::array<RTLIL::SigSpec, 2>>::hash_into(inputs, h);
|
||||
h = assign_map(cell->getPort(ID::Y)).hash_into(h);
|
||||
} else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
|
||||
SigSpec a = assign_map(cell->getPort(ID::A));
|
||||
a.sort();
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue