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Add new tests for ice40 architecture

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This commit is contained in:
SergeyDegtyar 2019-08-20 07:50:05 +03:00
parent 749ff864aa
commit 153ec0541c
28 changed files with 901 additions and 0 deletions
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7
tests/ice40/memory.ys Normal file
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proc
memory
equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40
synth_ice40
select -assert-count 8 t:SB_DFF
select -assert-count 512 t:SB_DFFE
write_verilog ./temp/memory_synth.v