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functional backend: reduce $lcu to $alu
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@ -181,20 +181,14 @@ private:
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Node x = factory.bitwise_or(t2, t3);
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return {{ID(X), x}, {ID(Y), y}};
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}
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Node handle_lcu(Node p, Node g, Node ci) {
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Node rv = factory.bitwise_or(factory.slice(g, 0, 1), factory.bitwise_and(factory.slice(p, 0, 1), ci));
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Node c = rv;
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for(int i = 1; i < p.width(); i++) {
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c = factory.bitwise_or(factory.slice(g, i, 1), factory.bitwise_and(factory.slice(p, i, 1), c));
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rv = factory.concat(rv, c);
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}
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return rv;
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}
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dict<IdString, Node> handle_alu(Node a_in, Node b_in, int y_width, bool is_signed, Node ci, Node bi) {
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Node a = factory.extend(a_in, y_width, is_signed);
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Node b_uninverted = factory.extend(b_in, y_width, is_signed);
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Node b = factory.mux(b_uninverted, factory.bitwise_not(b_uninverted), bi);
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Node x = factory.bitwise_xor(a, b);
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// we can compute the carry into each bit using (a+b+c)^a^b. since we want the carry out,
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// i.e. the carry into the next bit, we have to add an extra bit to a and b, and
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// then slice off the bottom bit of the result.
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Node a_extra = factory.extend(a, y_width + 1, false);
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Node b_extra = factory.extend(b, y_width + 1, false);
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Node y_extra = factory.add(factory.add(a_extra, b_extra), factory.extend(ci, a.width() + 1, false));
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@ -203,6 +197,9 @@ private:
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Node co = factory.slice(carries, 1, y_width);
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return {{ID(X), x}, {ID(Y), y}, {ID(CO), co}};
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}
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Node handle_lcu(Node p, Node g, Node ci) {
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return handle_alu(g, factory.bitwise_or(p, g), g.width(), false, ci, factory.constant(Const(State::S0, 1))).at(ID(CO));
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}
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public:
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std::variant<dict<IdString, Node>, Node> handle(IdString cellType, dict<IdString, Const> parameters, dict<IdString, Node> inputs)
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{
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